System and method of oversampling high speed clock/data...

Details System and method of oversampling high speed clock/data... System and method of oversampling high speed clock/data...

2007-03-20

2007-03-20

Nguyen, Linh (Department: 2819)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S376000, C375S355000

Reexamination Certificate

active

11312694

ABSTRACT:
A system and method of high speed clock/data recovery, which is used to recover the high speed clock/data through oversampling technique, wherein the internal clock with frequency lower than the high speed data is used for data recovery. Only three clocks are used in the digital circuit without involving all the oversampling clock phases to make the design timing complicated and critical. The system and method provide a simple clock structure to implement the digital circuit of high speed clock/data recovery in a robust and easy way. Furthermore a phase selection mechanism which decides the clock phase of the high speed data is provided as well.

REFERENCES:
patent: 6266799 (2001-07-01), Lee et al.
patent: 6340910 (2002-01-01), Saeki
patent: 6775345 (2004-08-01), Song
patent: 6838945 (2005-01-01), Song
patent: 7010074 (2006-03-01), Nakamura
patent: 2002/0085657 (2002-07-01), Boerstler
patent: 2002/0154723 (2002-10-01), Nakamura
patent: 2004/0202261 (2004-10-01), Gregorius

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