Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2008-04-22
2008-04-22
Lane, Jack (Department: 2185)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S150000, C711S170000
Reexamination Certificate
active
07363459
ABSTRACT:
A method of storing data includes the steps of storing data comprising the steps of identifying respective lifetimes of each member of an indexed collection of data elements, each of the data elements referenceable in a data index space representing a set of valid data element indices; identifying a set of pairs of the data elements having overlapping lifetimes; and generating a mapping from the data index space to an address offset space based on the set of pairs of the data elements having the overlapping lifetimes.
REFERENCES:
patent: 4991088 (1991-02-01), Kam
patent: 5764951 (1998-06-01), Ly et al.
patent: 6078745 (2000-06-01), De Greef et al.
patent: 6298071 (2001-10-01), Taylor et al.
patent: 6374403 (2002-04-01), Darte et al.
patent: 6438747 (2002-08-01), Schreiber et al.
patent: 2004/0034754 (2004-02-01), Schreiber
patent: 2004/0088515 (2004-05-01), Schreiber et al.
patent: 2004/0088520 (2004-05-01), Gupta et al.
U.S. Appl. No. 10/223,224, Schreiber.
U.S. Appl. No. 10/284,932, Schreiber, et al.
U.S. Appl. No. 10/284,965, Gupta, et al.
R. Schreiber, et al. “PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators,” Journal of VLSI Signal Processing, to appear.Hewlett-Packard Laboratories, Palo Alto, California 94304-1126, pp. 1-22.
J. Steensma, et al., “Symbolic Macro Test for DSP Systems Applied to a Voice Coder Application,” pp. 215-223.
Christine Eisenbeis, et al., “A Strategy for Array Management in Local Memory,” (Jul. 1990), pp. 1-40.
A. Agarwal, et al., “Automatic Partitioning of Parallel Loops and Data Arrays for Distributed Shared Memory Multiprocessors,” pp. 1-41.
J. Rosseel, et al., “An Optimisation Methodology for Array Mapping of Affine Recurrence Equations in Video and Image Processing,” IEEE, pp. 415-426 (1994).
S. Malik, “Analysis of Cyclic Combinational Circuits,” Short Papers IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, vol. 13, No. 7, (Jul. 1994) pp. 950-956.
A. Srinivasan, et al. “Practical Analysis of Cyclic Combinational Circuits,” IEEE 1996 Custom Integrated Circuits Conference, pp. 381-384.
Guest Editorial, IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, vol. 18, No. 1, (Jan. 1999) pp. 1-2.
K. Danckaert, et al. “Strategy for Power-Efficient Design of Parallel Systems,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 7, No. 2, (Jun. 1999) pp. 258-265.
F. Vermeulen, et al., “Extended Design Reuse Trade-Offs in Hardware-Software Architecture Mapping,” (2000) pp. 103-107.
R. Schreiber, et al., “High-Level Synthesis of Nonprogrammable Hardware Accelerators,” IEEE (2000) pp. 1-12.
S. Mahlke, et al., “Bitwidth Cognizant Architecture Synthesis of Custom Hardware Accelerators,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, No. 11, (Nov. 2001) pp. 1355-1371.
P. R. Panda, et al., “Data and Memory Optimization Techniques for Embedded Systems,” ACM Transactions on Design Automation of Electronic Systems, vol. 6, No. 2, (Apr. 2001) pp. 149-206.
S. Meftali, et al., “An Optimal Memory Allocation for Application-Specific Multiprocessor System-on-Chip,” (2001) pp. 19-24.
T. Van Achteren, et al., “Data Reuse Exploration Techniques for Loop-dominated Applications,” Proceedings of the 2002 Design, Automation and Test in Europe Conference and Exhibition , IEEE Computer Society, (Jan. 2002).
“Omega Project Source Release, version 1.2 (Aug. 2002),” [on-line] [retrieved on : Jul. 16, 2002], Retrieved from: http://www.cs.umd.edu/projects/omega/release-1.2.html, pp. 1-2.
Seeds for Tomorrow's World—IMECnology, [on-line] [Retrieved on Jun. 12, 2002] Retrived from: http://www.Imec.be/.
G. Havas, et al. “Extended GCD and Hermite Normal Form Algorithms Via Lattice Basis Reduction,” Experimental Mathmatics, v. 7 (1998).
Eddy De Greef, Francky Catthoor, and Hugo De Man, Memory Size Reduction Through Storage Order Optimization for Embedded Parallel Multimedia Applications, Parallel Computing, 1997, 23(12):1811-1837, North-Holland, Amsterdam, Netherlands.
Fabien, Quilleré and Sanjay Rajopadhye, Optimizing Memory Usage in the Polyhedral Model, ACM Transactions on Programming Languages and Systems, 2000, 22(5)773-815, ACM Press, New York.
Vincent Lefebvre and Paul Feautrier, Automatic Storage Management for Parallel Programs, Parallel Computing, 1998, 24(3-4): 649-671, North-Holland, Amsterdam, Netherlands.
Alain Darte, Robert Schreiber, and Gilles Villard, Lattice-Based Memory Allocation, Proceedings of the 2003 International Conference on Compilers, Architectures, and Synthesis for Embedded Systems, pp. 298-308, Oct. 2003, ACM PRESS, New York.
Panda, P R etal—“Efficient Utilization of Scratch-Pad Memory in Embedded Processor Applications”—Mar. 17, 1007—pp. 7-11.
Kandemir, M et al—“Compiler-Directed Selection of Dynamic Memory Layouts”—Apr. 25, 2001—pp. 219-224.
Grun, P et al—“APEX: Access Pattern Based Memory Architecture Exploration”—Sep. 30, 2001—pp. 25-32.
Catthoor, F et al—“Hot Topic Session: How to Solve the Current Memory Access and Data Transfer Bottlenecks . . . ”—Mar. 27, 2000—pp. 426-433.
Kandemir, M et al—Exploiting Scratch-Pad Memory Using Presburger Formulas—Sep. 30, 2001—pp. 7-12.
McFarland, MC et al—“The Hogh-Level Synthesis of Digital Systems”—Proc of the IEEE vol. 78 No. 1—Feb. 1, 1990—pp. 301-318.
Park, N et al—Sehwa: A Software Package for Synthesis of Pipelines From Behavioral Specifications—IEEE Transactions vol. 7 No. 3—Mar. 1998—pp. 356-370.
Darte Alain
Schreiber Robert S.
Hewlett--Packard Development Company, L.P.
Lane Jack
LandOfFree
System and method of optimizing memory usage with data... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method of optimizing memory usage with data..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method of optimizing memory usage with data... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2751746