Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2011-04-12
2011-04-12
Bragdon, Reginald G (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S148000, C711S103000, C711S104000, C711SE12084, C714S048000, C710S009000
Reexamination Certificate
active
07925854
ABSTRACT:
A memory system architecture is provided in which a memory controller controls memory devices in a serial interconnection configuration. The memory controller has an output port for sending memory commands and an input port for receiving memory responses for those memory commands requisitioning such responses. Each memory device includes a memory, such as, for example, NAND-type flash memory, NOR-type flash memory, random access memory and static random access memory. Each memory command is specific to the memory type of a target memory device. A data path for the memory commands and the memory responses is provided by the interconnection. A given memory command traverses memory devices in order to reach its intended memory device of the serial interconnection configuration. Upon its receipt, the intended memory device executes the given memory command and, if appropriate, sends a memory response to a next memory device. The memory response is transferred to the memory controller.
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Kim Jin-Ki
Oh HakJune
Pyeon Hong Beom
Borden Ladner Gervais LLP
Bragdon Reginald G
Hung Shin
Mosaid Technologies Incorporated
Talukdar Arvind
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