Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-07-02
2010-06-15
Whitmore, Stacy A (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07739627
ABSTRACT:
A system and a method of creating context dependent yield variants of integrated circuit (“IC”) design components and using these variants during a physical design of an IC block to maximize manufacturing yield are described. A plurality of variants of each design component is generated and characterized with manufacturing yield as a function of neighboring context (“context”) that includes, but is not limited to, neighboring design components and other layout objects and shapes. The present invention describes a system and method where a physical design process, in addition to satisfying design and performance requirements such as, but not limited to, power, timing, signal integrity and minimal layout area, selects context dependent yield variants to maximize manufacturing yield.
REFERENCES:
patent: 6851101 (2005-02-01), Kong et al.
patent: 2005/0114824 (2005-05-01), Wang et al.
patent: 2005/0246674 (2005-11-01), Scheffer
patent: 2008/0028353 (2008-01-01), Lu et al.
Chew Marko P.
Yang Yue
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