Electrical computers and digital processing systems: processing – Processing control – Instruction modification based on condition
Reexamination Certificate
2011-07-19
2011-07-19
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Instruction modification based on condition
Reexamination Certificate
active
07984277
ABSTRACT:
A method and system of instruction modification. A first machine language instruction, which may comprise a plurality of discrete instructions, is fetched. Responsive to a trigger pattern in the first machine language instruction, a segment of the first machine language instruction is modified. Information can be substituted into the segment based on specifics outlined in the trigger pattern. Alternatively, information can be combined with the segment via logical and/or arithmetic operations. Modification of the segment produces a second machine language instruction that is executed by units of the processor. In one embodiment, information may be taken from a queue and used to replace data from the segment. How information is taken from the queue and how the information so taken is used to replace fields of the segment are defined by the trigger pattern.
REFERENCES:
patent: 4050058 (1977-09-01), Garlic
patent: 4199811 (1980-04-01), Borgerson et al.
patent: 4259718 (1981-03-01), Kaman et al.
patent: 4312036 (1982-01-01), Porter et al.
patent: 4314331 (1982-02-01), Porter et al.
patent: 4342078 (1982-07-01), Tredennick et al.
patent: 4371908 (1983-02-01), Andow et al.
patent: 4371927 (1983-02-01), Wilhite et al.
patent: 4376976 (1983-03-01), Lahti et al.
patent: 4394736 (1983-07-01), Bernstein et al.
patent: 4399505 (1983-08-01), Druke et al.
patent: 4591972 (1986-05-01), Guyer et al.
patent: 4654781 (1987-03-01), Schwartz et al.
patent: 4745544 (1988-05-01), Renner et al.
patent: 4763246 (1988-08-01), Holt et al.
patent: 4825363 (1989-04-01), Baumann et al.
patent: 4875160 (1989-10-01), Brown, III
patent: 4928223 (1990-05-01), Dao et al.
patent: 4933847 (1990-06-01), Chau et al.
patent: 5005118 (1991-04-01), Lenoski
patent: 5057837 (1991-10-01), Colwell et al.
patent: 5101344 (1992-03-01), Bonet et al.
patent: 5115500 (1992-05-01), Larsen
patent: 5129066 (1992-07-01), Schmookler
patent: 5129067 (1992-07-01), Johnson
patent: 5153881 (1992-10-01), Bruckert et al.
patent: 5168571 (1992-12-01), Hoover et al.
patent: 5179680 (1993-01-01), Colwell et al.
patent: 5202967 (1993-04-01), Matsuzaki et al.
patent: 5220656 (1993-06-01), Itomitsu et al.
patent: 5222244 (1993-06-01), Carbine et al.
patent: 5233694 (1993-08-01), Hotta et al.
patent: 5235686 (1993-08-01), Bosshart
patent: 5291494 (1994-03-01), Bruckert et al.
patent: 5293592 (1994-03-01), Fu et al.
patent: 5301341 (1994-04-01), Vassiliadis et al.
patent: 5325495 (1994-06-01), McLellan
patent: 5341497 (1994-08-01), Younger
patent: 5371844 (1994-12-01), Andrew et al.
patent: 5418970 (1995-05-01), Gifford
patent: 5485629 (1996-01-01), Dulong
patent: 5555428 (1996-09-01), Radigan et al.
patent: 5559974 (1996-09-01), Boggs et al.
patent: 5566298 (1996-10-01), Boggs et al.
patent: 5649135 (1997-07-01), Pechanek et al.
patent: 5784585 (1998-07-01), Denman
patent: 5832205 (1998-11-01), Kelly et al.
patent: 5857103 (1999-01-01), Grove
patent: 5862398 (1999-01-01), Hampapuram et al.
patent: 5867681 (1999-02-01), Worrell et al.
patent: 5925123 (1999-07-01), Tremblay et al.
patent: 5974539 (1999-10-01), Guttag et al.
patent: 6041399 (2000-03-01), Terada et al.
patent: 6044450 (2000-03-01), Tsushima et al.
patent: 6065106 (2000-05-01), Deao et al.
patent: 6092185 (2000-07-01), Slegel et al.
patent: 6101592 (2000-08-01), Pechanek et al.
patent: 6112299 (2000-08-01), Ebcioglu et al.
patent: 6202142 (2001-03-01), Narayan et al.
patent: 6202143 (2001-03-01), Rim
patent: 6230260 (2001-05-01), Luick
patent: 6282633 (2001-08-01), Killian et al.
patent: 6317872 (2001-11-01), Gee et al.
patent: 6343373 (2002-01-01), Koizumi et al.
patent: 6397379 (2002-05-01), Yates, Jr. et al.
patent: 6442701 (2002-08-01), Hurd
patent: 6453407 (2002-09-01), Lavi et al.
patent: 6571386 (2003-05-01), Figurin et al.
patent: 6618804 (2003-09-01), Steele, Jr. et al.
patent: 6658551 (2003-12-01), Berenbaum et al.
patent: 6871274 (2005-03-01), Nunomura
patent: 2004/0230777 (2004-11-01), Busaba et al.
Hennessy, John L. et al., Computer Architecture A Quantitative Approach, 1996, Morgan Kaufmann Publishers, Inc., 2nd Ed., pp. 130 and 284-289.
Ozer et al., A Fast Interrupt Handling Scheme for VLIW Processors, Oct. 12-18, 1998, Proceedings of International Conference on Parallel Architectures and Compilation Techniques, pp. 136-141.
Title: A VLIW architecture for a trace scheduling compiler, author: Colwell et al, ACM, 1987.
Title: Architecture and compiler tradeoffs for a long instruction wordprocessor, author: Cohn et al, ACM 1989.
Title: Combining as a compilation technique for VLIW architectures, Author: Nakatani et al, ACM, 1989.
Title: Core-Based RNS ALU with customized instructions, author: Ray, IEEE, 1990.
Title: RISC I: a reduced instruction set VLSI computer, author: Patterson, ACM, 1998.
Final Office Action Dated Jun. 25, 2003; Patent No: 6738892.
Non-Final Office Action Dated Apr. 11, 2002; Patent No. 6738892.
Non-Final Office Action Dated Dec. 20, 2002; Patent No. 6738892.
Final Office Action Dated May 2, 2003; Patent No. 6754892.
Non Final Office Action Dated Nov. 25, 2002; Patent No. 6754892.
Notice of Allowance Dated Oct. 27, 2003; Patent No. 6754892.
Notice of Allowance Dated Dec. 22, 2003; Patent No. 6738892.
Notice of Allowance Dated Jun. 10, 2009; Patent No. 7606997.
Advisory Action Dated Jul. 5, 2007; Patent No. 7606997.
Non Final Office Action Dated Dec. 9, 2005; Patent No. 7606997.
Non Final Office Action Dated Nov. 2, 2006; Patent No. 7606997.
Non Final Office Action Dated Sep. 17, 2007; Patent No. 7606997.
Amendment Dated Aug. 31, 2006; Patent No. 7606997.
Non Final Office Action Dated Aug. 4, 2008; Patent No. 7606997.
Final Office Action Dated Mar. 14, 2007; Patent No. 7606997.
Final Office Action Dated Mar. 6, 2008; Patent No. 7606997.
Final Office Action Dated Jan. 27, 2009; Patent No. 7606997.
Notice of Allowance Dated Oct. 30, 2009; Patent No. 7698539.
Final Office Action Dated Apr. 11, 2008; Patent No. 7698539.
Non Final Office Action Dated Apr. 13, 2009; Patent No. 7698539.
Non Final Office Action Dated Sep. 24, 2007; Patent No. 7698539.
Final Office Action Dated Dec. 20, 2006; Patent No. 7698539.
Non Final Office Action Dated Jun. 26, 2006; Patent No. 7698539.
:Examiner Interview Summary Dated Apr. 1, 2009; Patent No. 7606997.
Final Office Action Dated May 31, 2006; Patent No. 7606997.
TRANSMETA P2000 (project name: Fred); Instruction Set Architecture and Programmer's Reference Manual. Version 1.01 Jun. 28, 2001.
Williams Stalling, Ph.D; Data and Computer Communications; Third Edition. Macmillan Publishing Company. New York, New York. 1991.
Val Popescu; et al. The Metaflow Architecture; 1991.
Enterprise Systems Architecture/390 Principles of Operation. Eight Edition, Jul. 2001. pp. 7-1 to 7-5, 9-1 to 9-4 and 9-8 to 9-9.
Mike Johnson. Superscalar Microprocessor Design. 1991 by PTR Prentice-Hall, In., A Pearson Education Company Upper Saddle River, NJ 07458.
Banning John
Coon Brett
Hao Eric
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