System and method of identifying liveness groups within...

Details System and method of identifying liveness groups within... System and method of identifying liveness groups within...

2006-02-21

2006-02-21

Nguyen, Hiep T. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C712S233000

Reexamination Certificate

active

07003629

ABSTRACT:
A microprocessor may include a trace cache and a trace generator. The trace cache includes several trace cache entries. Each trace cache entry is configured to store several operations and a respective set of liveness indications. The operations are generated by at least partially decoding several instructions. The trace generator may be configured to generate the respective plurality of liveness indications for the operations stored in each trace cache entry. Each liveness indication identifies whether its respective operation depends on a branch operation stored within that trace cache entry.

REFERENCES:
patent: 2004/0143721 (2004-07-01), Pickett et al.
Yuan Chou, et al., “Instruction Path Coprocessors,” Mar. 2000, pp. 1-24.
Friendly, et al., “Putting the Fill Unit to Work: Dynamic Organizations for Trace Cache Microprocessors,” Dept. of Electrical Engineering and Computer Sciences, The Univ. of Michigan, Dec. 1998, 9 pages.
Bryan Black, et al., “Turboscalar: A High Frequency High IPC Microarchitecture,” Dept. of Electrical and Computer Engineering, Carnegie Mellon Univ., Jun. 2000, pp. 1-.
Rotenberg, et al., “Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching,” Apr. 11, 1996, pp. 1-48.
Merten, et al., “An Architectural Framework for Run-Time Optimization,” Jun. 2001, pp. 1-43.
Jourdan, et al., “Increasing the Instruction-Level Parallelism through Data-Flow Manipulation,” Intel, 11 pages.

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