Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing
Reexamination Certificate
2011-04-12
2011-04-12
Rossoshek, Helen (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Logic design processing
C716S103000, C716S104000, C716S106000, C716S113000, C716S117000, C716S134000, C716S138000, C716S139000
Reexamination Certificate
active
07926011
ABSTRACT:
A system and method of designing an integrated circuit capable of deriving timing constraints for individual block-level circuits of an integrated circuit that are derived from the chip-level timing constraints and analysis. The block-level timing constraints are in the form of one or more logical timing constraint points at the input and output ports of block-level circuits. Each logical timing constraint points specifies a clock source used to clock data through the port, a delay parameter specifying data propagation delay backward from an input port and forward from an output port, and any timing exception associated with the data path. Using the logical timing constraint point, the circuit design system performs independent timing analysis and optimization of each block-level circuit. The system then reassembles the block-level circuits into a modified chip-level circuit for which timing closure can be achieved.
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Gupta Dinesh
Kuo Chien-Chu
Levitsky Oleg
Alford William E.
Alford Law Group, Inc.
Cadence Design Systems Inc.
Fountain George L.
Rossoshek Helen
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