Semiconductor device manufacturing: process – With measuring or testing – Electrical characteristic sensed
Reexamination Certificate
2003-06-13
2004-11-02
Pert, Evan (Department: 2829)
Semiconductor device manufacturing: process
With measuring or testing
Electrical characteristic sensed
C324S071100
Reexamination Certificate
active
06812050
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to semiconductor electronic circuits and, more particularly, to a system and method for evaluating gate oxide integrity for semiconductor microchips.
Gate oxide integrity (GOI) is a critical metric for the effective functioning of the transistor. With scaling of devices the gate oxides have become thinner to the extent that present day devices use oxides on the range 12-24 Angstroms. This makes them more susceptible to defects which are detrimental to eventual yield of the devices, Defects cause enhanced leakage and eventually premature (non-intrinsic) breakdown of oxides. The GOI integrity needs to be evaluated early in the device processing in the front end of the line to prevent unnecessary, wasteful utilization of time and resources in the back end of the line (BEOL). Present methods use an in-line invasive probe on a few sampled sites to determine current-voltage characteristics and from it to assess gate oxide quality or health.
Currently, there is not a good non-contact system or method to test gate oxide integrity during the semiconductor microchip manufacture itself. All existing methods use probes to test the gate oxide integrity after the semiconductor processing is completed (End of line). In addition, the probes or methods used in the current test systems can introduce contamination on the semiconductor wafers. Moreover, the testing systems only test a small set of specific sites on the semiconductor wafer. Thus they do not provide any wafer-spatial signature information. Active feedback of any spatial yield loss because of gate oxide integrity degradation is critical. Lack thereof results in continued faulty processing.
Therefore, what is needed, is a non-invasive system and method that tests gate oxide integrity, in-line amidst the different semiconductor processes. The method also needs to be fast, efficient, with more wafer spatial signature information, in order to provide active feedback and thus control process excursions and thus reduce yield loss.
SUMMARY OF THE INVENTION
The present disclosure provides a system and method that provides an improved method of inline evaluation of gate oxide integrity using electron beams.
The present invention provides a system and method for evaluating gate oxide integrity using electronic elements in a semiconductor wafer. The system may include: a semiconductor substrate on the semiconductor wafer; a layer of gate oxide on the semiconductor substrate; a layer of polysilicon on the gate oxide; an electron beam microscope with adjustable energy levels, wherein the electron beam microscope is directed at the semiconductor wafer; an electron beam inspection tool used to detect contrasts within the gate oxide layer. The system may also include a measuring tool for measuring an electrical current level of the semiconductor substrate. The system may also include an electrical ground connected to the semiconductor wafer. The system may also include the electron beam energy levels vary from about 600 volts to 5000 volts.
Therefore, in accordance with the previous summary, objects, features and advantages of the present disclosure will become apparent to one skilled in the art from the subsequent description and the appended claims taken in conjunction with the accompanying drawings.
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Cappel et al., “The Advantages of In-Line Electron-Beam Wafer Inspection,” Summer 2000, Yield Management Solutions, pp. 8-12.*
Liang et al., “Rapid in-line characterization of plasma-induced damage on a 0.25 um CMOS ASIC technology,” Jun. 1998, 3rd International Symposium on Plasma Process-Induced Damage, 1998, pp. 148-151.*
Colvin, “A New Technique to rapidly Identify Gate Oxide leakage in Field Effect Semiconductors Using a Scanning Electron Microscope,” 1990, EOS/ESD Syposium Proceedings, pp. 173-176.
Brady III Wade James
Pert Evan
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Tung Yingsheng
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