Data processing: measuring – calibrating – or testing – Testing system – Signal generation or waveform shaping
Reexamination Certificate
2008-01-08
2008-01-08
Bui, Bryan (Department: 2863)
Data processing: measuring, calibrating, or testing
Testing system
Signal generation or waveform shaping
Reexamination Certificate
active
07318003
ABSTRACT:
According to one embodiment of the present invention, a system for identifying a running speed of an integrated circuit is provided. An asynchronous multi-rail circuit is configured to receive input data and transmit output data. A completion detection circuit is configured to generate a completion detection signal for the asynchronous multi-rail circuit. A variable clock generator configured to be driven by at least the completion detection signal. A synchronous circuit element configured to receive at least a portion of the output data and configured to be clock driven by a clock signal from the variable clock generator. A period of the clock signal represents a running speed of the asynchronous circuit.
REFERENCES:
patent: 4686392 (1987-08-01), Lo
patent: 5250856 (1993-10-01), Burton et al.
patent: 5305463 (1994-04-01), Fant et al.
patent: 5845109 (1998-12-01), Suzuki et al.
patent: 6043674 (2000-03-01), Sobelman
patent: 6075389 (2000-06-01), Umemoto et al.
patent: 6088830 (2000-07-01), Blomgren et al.
patent: 6133761 (2000-10-01), Matsubara
patent: 6509761 (2003-01-01), Taki
patent: 6526542 (2003-02-01), Kondratyet
patent: 6807509 (2004-10-01), Bourdin
patent: 6819150 (2004-11-01), Santosa et al.
patent: 6964003 (2005-11-01), Thibeault
patent: 2005/0007165 (2005-01-01), Sadowski
I. Blunno, J. Cortadella, A. Kondratyev, L. Lavagno, K. Lwin, and C. Sotiriou. Handshake Protocols for De-Synchronization. InProc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 149-158, IEEE Computer Society Press, Apr. 2004.
User Guide. InCeltic User Manual, Cadence Design Systems, Inc., 2004.
D. Chinnery and K. Keutzer. Reducing the Timing Overhead. InClosing the Gap between ASIC and Custom: Tools And Techniques For High-Performance ASIC Design, chapter 3. Kluwer Academic Publishers, 2002.
J. Cortadella, A. Kondratyev, L. Lavagno, and C. Sotiriou. Coping with the Variability of Combinational Logic Delays. InProc. International Conf. Computer Design(ICCD), Oct. 2004.
S. Devedas and K. Keutzer. Synthesis of Robust Delay-Fault Testable Circuits: Theory.IEEE Trnasactions on Computer-Aided Design, 11(1):87-101, Jan. 1992.
Y. Kukimoto, R.K. Brayton, and P. Sawkar. Delay-Optimal Technology Mapping by DAG Covering. InDesign Automation Conference, pp. 348-351, 1998.
Alex Kondratyev and Kelvin Lwin. Design of Asynchronous Circuits by Synchronous CAD Tools. InProc. ACM/IEEE Design Automation Conference, Jun. 2002.
D. S. Kung. Hazard-Non-Increasing Gate-Level Optimization Algorithms. InProc. International Conf. Computer-Aided Design(ICCAD), pp. 631-634, 1992.
E. Lehman, Y. Watanabe, J. Grodstein, H. Harkness. Logic Decomposition During Technology Mapping.Ieee Transactions On Computer-Aided Design, 16(8):813-834, Aug. 1997.
S.R Nassif. Modeling and Analysis of Manufacturing Variations. InProc. Of Asia And South Pacific Design Automation Conference, May 2001.
R. Puri, A. Bjorksten, and T. Rosser. Logic Optimization by Output Phase Asssignment in Dynamic Logic Synthesis. InProc. International Conf. Computer-Aided Design(ICCAD), pp. 2-8, 1996.
M. Prasad, D. Kirkpatrick, R.Brayton, and A. Sangiovanni Vincentelli. Domino. Logic Synthesis And Technology Mapping. InProc. International Workshop on Logic Synthesis, vol. 1, 1997.
Jens Sparsø and Jørgen Staunstrup. Delay-Insensitive Multi-Ring Structures.Integration, the VLSI journal, 15(3):313-340, Oct. 1993.
E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. Sangiovanni-Vincentelli, SIS: A System For Sequential Circuit Synthesis. Technical report, U.C. Berkeley, May 1992.
Ivan E. Sutherland. Micropipelines.Communications of the ACM, 32(6):720-738, Jun. 1989.
M. A. Thornton, K. Fazel, R. B. Reese, and C. Traver. Generalized Early Evaluation In Self-Timed Circuits. InProc. Design, Automation and Test in Europe(DATE), pp. 255-259, Mar. 2002.
S. H. Unger. Asynchronous Sequential Switching Circuits. Wiley-Interscience, John Wiley & Sons, Inc., New York, 1969.
Victor I. Varshavsky, editor.Self-Timed Control of Concurrent Processes: The Design of Aperiodic Logical Circuits in Computers and Discrete Systems. Kluwer Academic Publishers, Dordrecht, The Netherlands, 1990, Chapters 3 and 4.
R. K. Brayton et al, Multilevel Logic Synthesis, Proceedings of the IEEE, vol. 78, No. 2, Feb. 1990.
Bui Bryan
Institute of Computer Science, Foundation for Research and Techn
Steptoe & Johnson
Sun Xiuqin
LandOfFree
System and method of determining the speed of digital... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method of determining the speed of digital..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method of determining the speed of digital... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2806179