Abrading – Abrading process – Glass or stone abrading
Reexamination Certificate
1999-12-20
2002-08-13
Rachuba, M. (Department: 3723)
Abrading
Abrading process
Glass or stone abrading
C451S065000, C451S287000, C451S307000
Reexamination Certificate
active
06431959
ABSTRACT:
BACKGROUND
Semiconductor wafers are typically fabricated with multiple copies of a desired integrated circuit design that will later be separated and made into individual chips. A common technique for forming the circuitry on a semiconductor is photolithography. Part of the photolithography process requires that a special camera focus on the wafer to project an image of the circuit on the wafer. The ability of the camera to focus on the surface of the wafer is often adversely affected by inconsistencies or unevenness in the wafer surface. This sensitivity is accentuated with the current drive toward smaller, more highly integrated circuit designs. Semiconductor wafers are also commonly constructed in layers, where a portion of a circuit is created on a first level and conductive vias are made to connect up to the next level of the circuit. After each layer of the circuit is etched on the wafer, an oxide layer is put down allowing the vias to pass through but covering the rest of the previous circuit level. Each layer of the circuit can create or add unevenness to the wafer that is preferably smoothed out before generating the next circuit layer.
Chemical mechanical planarization (CMP) techniques are used to planarize the raw wafer and each layer of material added thereafter. Available CMP systems, commonly called wafer polishers, often use a rotating wafer holder that brings the wafer into contact with a polishing pad moving in the plane of the wafer surface to be planarized. A polishing fluid, such as a chemical polishing agent or slurry containing microabrasives, is applied to the polishing pad to polish the wafer. The wafer holder then presses the wafer against the rotating polishing pad and is rotated to polish and planarize the wafer.
Chemical mechanical planarization or polishing of polysilicon films is commonly used at different stages in the integrated circuit (IC) manufacturing process. These different stages can be roughly lumped into two categories: (i) smoothing of blanket polysilicon films as an intermediate step to ease further device processing, and (ii) formation of polysilicon filled plugs and trenches for local interconnect, capacitors and isolation needs.
In the case of a blanket film smoothing, some main characteristics of the CMP process are: uniformity of the remaining film, surface roughness of the film, and the final defect level after post-CMP cleaning. For the polysilicon plug or trench formation, some important parameters are polysilicon dishing, oxide erosion, and the quality of both polysilicon and oxide films. In both cases, the surface roughness of the remaining polysilicon film needs to be minimized during the CMP step, and the post-CMP cleaning process should provide low defect level without degrading surface roughness.
Accordingly, a polishing and cleaning process that is capable of providing low surface roughness and a low incidence of surface defects is desirable.
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Mikhaylich Katrina
Ravkin Michael
Brinks Hofer Gilson & Lione
Lam Research Corporation
Rachuba M.
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