Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2008-04-29
2011-12-13
Torres, Juan A (Department: 2611)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
Reexamination Certificate
active
08077822
ABSTRACT:
An apparatus comprising a programmable frequency device adapted to generate a reference clock selected from a set of distinct frequency clocks, wherein the programmable frequency device is further adapted to maintain the same temporal relationship of the triggering edges of the reference clock when switching between the distinct frequency clocks. The apparatus further comprises a phase locked loop (PLL), such as a digital PLL (DPLL), that uses the selected reference clock to establish a predetermined phase relationship between an input signal and an output signal. By maintaining substantially the same temporal relationship of the reference clock when switching between distinct frequency clocks, the continual and effective operation of the phase locked loop (PLL) is not significantly disturbed while changing the reference clock. This may be used to control the power consumption of the apparatus.
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International Search Report & Written Opinion—PCT/US2009/042105, International Search Authority—European Patent Office—Jul. 22, 2009.
Ballantyne Gary John
Sahota Gurkanwal Singh
Sun Bo
Moskowitz Larry J.
QUALCOMM Incorporated
Torres Juan A
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