Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-06-15
2008-11-04
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C700S121000
Reexamination Certificate
active
07448017
ABSTRACT:
A method and system is provided to use the same design manipulation processes for both chip design and kerf design. Concurrent generation of kerf designs and chip designs provides a consistent, accurate, and repeatable process. Improved quality of wafer testing results because the data in the kerf matches data in the chip. The total cycle time for mask manufacturing is reduced because kerf build is accomplished prior to start of the mask manufacturing process. Also provided is the use of load balancing across multiple servers during kerf and chip design to optimize computing resources.
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Barrett Howard T.
Bouchard Pierre J.
Clairmont James B.
Edwards Karen S.
McFadden Maureen F.
Dimyan Magid Y
Greenblum & Bernstein P.L.C.
International Business Machines - Corporation
Kotulak Richard
Siek Vuthe
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