System and method of acquiring delay, setup and hold values...

Details System and method of acquiring delay, setup and hold values... System and method of acquiring delay, setup and hold values...

2005-02-08

2005-02-08

Garbowski, Leigh M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06854102

ABSTRACT:
The method of the present invention acquires delay, setup and hold values that appropriately reflect the timing characteristics of an integrated circuit represented by a cell file. A data and clock input slope pair is selected and the data setup time value is swept with respect to the clock. For each setup value a corresponding hold value is determined for functional failure. Then for each setup and hold value pair a delay value is ascertained. In one exemplary implementation optimal delay, setup and hold values are determined and utilized to facilitate higher frequency designs using the same physical cell layout library.

REFERENCES:
patent: 5555187 (1996-09-01), Spyrou
patent: 5740347 (1998-04-01), Avidan

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