System and method having processor with selectable burst or no-b

Details System and method having processor with selectable burst or no-b System and method having processor with selectable burst or no-b

1994-08-29

1997-09-16

Lee, Thomas C.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

395886, 711143, C06F 1300

Patent

active

056690142

ABSTRACT:
A processor for processing information is described. The processor can select between a write-burst mode of transferring information and an individual write cycle mode of transferring information. The write-burst mode of transferring information is a transfer of information in a single burst transaction and the individual write cycle mode of transferring information is a transfer of information in separate write cycles.

REFERENCES:
patent: 4677548 (1987-06-01), Bradley
patent: 5101498 (1992-03-01), Ehlig et al.
patent: 5146582 (1992-09-01), Begun
patent: 5247643 (1993-09-01), Shottan
patent: 5262990 (1993-11-01), Mills et al.
patent: 5375216 (1994-12-01), Moyer et al.
patent: 5469544 (1995-11-01), Aatresh et al.

Affiliated with

Also associated with

Rating

System and method having processor with selectable burst or no-b does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System and method having processor with selectable burst or no-b, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method having processor with selectable burst or no-b will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-226540