System and method for zeroing pages with cache line invalidate i

Details System and method for zeroing pages with cache line invalidate i System and method for zeroing pages with cache line invalidate i

1996-08-30

1998-09-15

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

711136, 711144, 711135, 711133, G06F 1212

Patent

active

058095489

ABSTRACT:
A check is made to determine if a copy of a cache line is currently resident in the level-one data cache of a microprocessor system. If, in response to the check, it is determined that a copy of such cache line in fact is not currently resident, the cache line is created as the least-recently used cache line. Then, for set-associative data caches, the next used of the associative set will replace the most recently zeroed line. In this way, zeroing operations can replace only one .div. (number of associative sets) of the data cache for zeroing operations, thereby leaving the most frequently used data intact. By doing so, the data-cache is not wasted on zeroed cache lines which may be infrequently reused from the data cache, thereby significantly improving system performance. In other words the net effect is to reduce probability of data cache misses on subsequent instructions because more of the cache is thereby made available for more frequently reused data. The state of the cache is better preserved without creating performance losses exhibited by the previous technique. In a preferred embodiment, the hereinbefore described system and method is employed in systems with processors comprising substantial writeback queues and memory subsystems permitting numerous outstanding writes to be in progress, and is further employed in systems embodying cache line zero/invalidate instructions.

REFERENCES:
patent: 4197580 (1980-04-01), Chang et al.
patent: 4442488 (1984-04-01), Hall
patent: 4467411 (1984-08-01), Fry et al.
patent: 4885680 (1989-12-01), Anthony et al.
patent: 4972368 (1990-11-01), O'Brien et al.
patent: 5113508 (1992-05-01), Groves et al.
patent: 5287481 (1994-02-01), Lin
patent: 5367653 (1994-11-01), Coyle et al.
patent: 5398325 (1995-03-01), Chang et al.
patent: 5418921 (1995-05-01), Cortney et al.
patent: 5423019 (1995-06-01), Lin
patent: 5434993 (1995-07-01), Liencres et al.
patent: 5517633 (1996-05-01), Ohta et al.
M. Rosenblulm et al, "The Impact of Architectural Trends on Operating System Performance", 1995, Association for Computing Machinery, Inc., pp. 1-14.
J. Chapin et al, "Memory System Performance of UNIX on CC-NUMA Multiprocessors", SIGMETRICS, 1995, ACM 0-89791-695/0005, pp. 1-13.
J. B. Chen et al, "The Impact of Operating System Structure on Memory System Performance", SIGOPS, 1993, ACM 0-89791-632-8/93/0012, pp. 120-133.
RISC System/6000 Technology, IBM Corporation, 1990, SA23-2619,00--pp. 16-23 and pp. 44-50.

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