Electrical computers and digital processing systems: memory – Address formation – Slip control – misaligning – boundary alignment
Reexamination Certificate
1999-01-08
2001-04-24
Lane, Jack A. (Department: 2751)
Electrical computers and digital processing systems: memory
Address formation
Slip control, misaligning, boundary alignment
C712S300000, C365S195000, C365S238500, C711S163000
Reexamination Certificate
active
06223268
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to improvements in memory addressing and specifically to a system and method for writing to arbitrary individual byte locations contained within a wide-word organized memory.
2. Description of the Background Art
Digital audio and digital video are two technologies that must rapidly manipulate vast amounts of data. A common architectural approach to facilitate this data manipulation is to organize the memory so that it transfers the data in wide words. In this manner, many bytes of data may be transferred simultaneously during a single memory access.
In an exemplary application, the controller for a Digital Video Disk (DVD) transfers data using a 64-bit wide word (i.e. a word containing eight 8-bit bytes). This memory architecture allows the rapid transfer of digital audio and digital video. However, the foregoing rapid transfer of data results in a significant loss of flexibility.
Digital audio and video are often transferred as a composite digital bitstream. Embedded within the digital audio and video bitstream may be additional information called auxiliary data. This auxiliary data may arrive at irregular times and consist of irregular numbers of bytes. For this reason, the auxiliary data may not be sent directly as it arrives to a synchronous dynamic-random-access-memory (SDRAM) in even multiples of eight bytes. Sending data to memory in non-even multiples of eight bytes at a time is not possible in the customary wide-word architecture. While the address word may contain address information capable of specifying individual bytes contained within a wide word, attempting to write to these individual bytes causes problems. If the data desired to be written does not evenly fit the eight-byte wide word, then attempting to write to any byte within that wide word causes unintended data writes into bytes other than the desired bytes. The result is that the desired data is successfully written, but the other bytes then contain corrupted data.
To avoid the foregoing, some systems add considerable additional logic to the circuit which receives the bitstream. This additional logic may include additional local data buffering and other circuitry. The local buffering allows for larger amounts of auxiliary data to accumulate prior to writing to wide-word memory. When a transfer of this buffered data to wide-word memory is desired, the additional logic first reads from the wide-word memory in the target area, then assembles wide-words which contain both the buffered data and the recently-read data which should remain undisturbed. When these wide-words are subsequently written to wide-word memory, the overall effect is to write specific bytes into the wide-word memory without corrupting adjacent bytes.
The above method does allow the writing of specific bytes into a wide-word memory, but at the cost of complexity. An exemplary implementation of the above additional logic added to the circuit which receives the bitstream requires on the order of 10,000 additional gates. Therefore, there exists a need for a system and method which allows directly writing specific bytes into a wide-word memory without the complexity of supporting additional buffering and attendant multiple memory accesses.
SUMMARY OF THE INVENTION
The present invention includes a system and method for writing specific bytes in a wide-word memory. In one embodiment of the present invention, a wide-word memory controller includes a memory arbitrator, a memory address generator, and a synchronous dynamic-random-access-memory (SDRAM) interface. In this embodiment, the memory address generator includes a data mask byte (DQM) logic for generating values for DQM. These DQMs include individual data mask bits numbered DQM
0
through DQM
7
. The individual DQM
0
through DQM
7
may inhibit writing to their corresponding byte locations within a wide-word in memory.
In one embodiment of the present invention, composite 32-bit memory addresses are used for data transfers. These 32-bit addresses contain a byte address field which may address individual bytes in a wide-word memory, and also a byte-count field for determining how many bytes remain to be transferred. The DQM logic calculates two values, called a start-mask and an end-mask, which are intended for use either individually or together as DQM values depending upon circumstances.
The memory arbitrator sends the memory address generator a 32-bit memory address. The DQM logic calculates the first start-mask by shifting 1111111100000000 to the right by an arithmetic combination of values in the 32-bit address, and then taking the eight least-significant bits. The DQM logic also calculates the first end-mask by shifting 0000000001111111 by another arithmetic combination of values in the 32-bit address, and then taking the eight least-significant bits. Then the DQM logic of the memory address generator determines whether the memory write operation includes only one, or more than one, wide-words by testing to see if a third arithmetic combination of values in the 32-bit address is less than 8.
If the answer is no, then the DQM logic determines that the current memory write operation contains multiple wide-words. Then the memory address generator sends the current start-mask as data mask bits DQM
0
through DQM
7
to the SDRAM interface, along with the current individual address. The SDRAM interface uses the current individual address and the data mask bits DQM
0
through DQM
7
to perform four 16-bit data write operations to external SDRAM, with two of the data mask bits being asserted during each 16-bit data write operation.
After the SDRAM interface has performed the four 16-bit data write operations, memory address generator then updates the byte count and byte address. Then the DQM logic calculates the current values for start-mask and end-mask. After updating these values, the DQM logic determines if the next wide-word is the last wide-word. If the answer is no, then the sub-process of memory writing with the current start-mask as data mask bits DQM
0
through DQM
7
repeats.
Conversely, if the answer is yes, then the memory address generator sends the current end-mask as data mask bits DQM
0
through DQM
7
to SDRAM interface along with the current individual address. The SDRAM interface uses the current individual address and the data mask bits DQM
0
through DQM
7
to perform four 16-bit data write operations to external SDRAM, with two of the data mask bits being asserted during each 16-bit data write operation. Because this is the last wide-word of the current memory write operation, the memory write operation then ends.
The above discussion assumes that the memory write operation covers multiple wide-words. Conversely, if the memory write operation covers only one wide-word, the DQM logic performs a bitwise-or function on the current start-mask and end-mask. The least-significant eight bits of the resulting word form the bit-or-mask for the memory write operation. Memory address generator then sends data mask bits DQM
0
through DQM
7
to SDRAM interface along with the individual address. The SDRAM interface uses the individual address and the data mask bits DQM
0
through DQM
7
to perform four 16-bit data write operations to external SDRAM, with two of the data mask bits being asserted during each 16-bit data write operation. Because there is only one wide-word considered in this memory write operation, the memory write operation then ends.
REFERENCES:
patent: 5241663 (1993-08-01), Rohwer
patent: 5465374 (1995-11-01), Dinkjian et al.
patent: 5553048 (1996-09-01), Maeda
patent: 5577228 (1996-11-01), Banerjee et al.
Lin Kuei-Cheng
Paluch, Jr. Edward John
Koerner Gregory J.
Lane Jack A.
Simon & Koerner LLP
Sony Corporation
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