System and method for write-enable bypass testing in an...

Details System and method for write-enable bypass testing in an... System and method for write-enable bypass testing in an...

2007-10-09

2007-10-09

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

Reexamination Certificate

active

10892049

ABSTRACT:
A system and method for write-enable bypass testing in an electronic circuit. According to one embodiment, the integrated circuit that includes a memory block having at least one input and at least one output. At least one input is associated with a block of input logic and at least one output is associated with a block of output logic. The integrated circuit also includes a test circuit coupled to the memory block and operable to verify the block of input logic and the block of output logic while at the same time not impacting the timing of the integrated circuit. As such a signal propagating through just the input logic, the memory block and the output logic does so in an amount of time substantially similar the time it takes to propagate through the input logic, the memory block, the output logic, and the test circuit.

REFERENCES:
patent: 2004/0120181 (2004-06-01), Fukatsu
patent: 2004/0128604 (2004-07-01), Guettaf

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