System and method for virtualizing processor and interrupt...

Details System and method for virtualizing processor and interrupt... System and method for virtualizing processor and interrupt...

2009-08-14

2011-10-11

Misiura, Brian (Department: 2111)

Electrical computers and digital data processing systems: input/

Interrupt processing

C710S262000, C710S264000, C710S266000, C718S001000, C718S100000, C718S103000

Reexamination Certificate

active

08037227

ABSTRACT:
Dispatching of interrupts to a processor is conditionally suppressed, that is, only if an old priority value and a new priority value are either both less than or both greater than a maximum pending priority value. This conditional avoidance of dispatching is preferably implemented by a virtual priority module within a binary translator in a virtualized computer system and relates to interrupts directed to a virtualized processor by a virtualized local APIC.

REFERENCES:
patent: 5727217 (1998-03-01), Young
patent: 5905897 (1999-05-01), Chou et al.
patent: 6298410 (2001-10-01), Jayakumar et al.
patent: 7426728 (2008-09-01), Ruemmler et al.

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