System and method for verifying signal propagation delays of...

Details System and method for verifying signal propagation delays of... System and method for verifying signal propagation delays of...

2007-10-16

2007-10-16

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C327S277000

Reexamination Certificate

active

10977635

ABSTRACT:
A system for verifying signal propagation delays of circuit traces of a printed circuit board (PCB) layout includes a computer (1). The computer includes: a setting module (10) for setting a minimum propagation delay and a maximum propagation delay for a trace to be verified, and making a selection regarding whether to calculate a propagation delay of a lead wire connected with the trace; a selecting module (11) for selecting a segment from a segment set of the trace; a calculating module (12) for calculating a propagation delay of the segment, the trace and the lead wire, and a total propagation delay; and a determining module (13) for determining whether all segments of the trace have been calculated, and whether the total propagation delay is between the minimum propagation delay and the maximum propagation delay. A related method is also disclosed.

REFERENCES:
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patent: 6349402 (2002-02-01), Lin
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patent: 2004/0207064 (2004-10-01), Brooks et al.
patent: 2006/0221686 (2006-10-01), Devadas et al.

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