System and method for verifying operation of a target system

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability

Reexamination Certificate

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C714S026000

Reexamination Certificate

active

08078915

ABSTRACT:
A system, a computer readable article of manufacture, and a method for verifying operation of a target system to be inspected. The system includes an abstract binary tree generation unit and a matching unit. The abstract binary tree generation unit obtains information about a functional specification of the target system and generates one or more binary trees that associate one or more states that can occur in the target system with respective nodes and that associate state transitions of objects constituting the target system and interactions between the objects with connection relationships between the nodes. The matching unit receives an event sequence in an application model of the target system obtained in response to the operation of the target system and matches the event sequence against the binary trees generated by the abstract binary tree generation unit. The method includes steps for accomplishing the functionality of the system.

REFERENCES:
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patent: 6907545 (2005-06-01), Ramadei et al.
patent: 7139676 (2006-11-01), Barford
patent: 7379846 (2008-05-01), Williams et al.
patent: 2006/0150018 (2006-07-01), Cousin et al.
Henrik Thane, “Debugging Using Time Machines: Replay Your Embedded Systems History”, Nov. 2001, Real-Time & Embedded Computing Conference, p. Kap 22, Milan, Italy.
Hans Hansson, “RTS Debugging”, Malardalen Real-Time Research Centre, 2003.

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