Error detection/correction and fault detection/recovery – Pulse or data error handling – Testing of error-check system
Reexamination Certificate
2006-03-28
2006-03-28
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Testing of error-check system
C714S052000, C714S746000, C714S758000
Reexamination Certificate
active
07020811
ABSTRACT:
A method of testing error correction/detection logic may involve providing each of a set of n data bit combinations to the error correction/detection logic. Each data bit combination has n bits, and the n data bit combinations may be created by creating an initial data bit combination whose data bits have the same logical value and then shifting a bit having the opposite value across the initial data bit combination. In response to being provided with the n data bit combinations, the error correction/detection logic generates a set of check bits for each of the n data bit combinations. The set of check bits generated by the error correction/detection logic for each of the n data bit combinations may then be verified.
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De'cady Albert
Gandhi Dipakkumar
Kowert Robert C.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Sun Microsystems Inc.
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