System and method for verifying data integrity

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique

Reexamination Certificate

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C714S779000

Reexamination Certificate

active

07426686

ABSTRACT:
A system for verifying data integrity includes a central processing unit (CPU) (1), a non-volatile random access memory (NVRAM) (2), and a program memory (3). The NVRAM includes: a plurality of data blocks (23), each data block including a plurality of data bits (20) for storing bit data; a first recognition bit (21) for storing a first recognition code; and a second recognition bit (22) for storing a second recognition code. The program memory stores program modules. The CPU updates and deletes data in data blocks, reads a first recognition code and a second recognition code in a data block in which bit data are to be read, and identifies whether the bit data are complete according to a combination of the first recognition code and the second recognition code. A related method for verifying data integrity is also disclosed.

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patent: 6185134 (2001-02-01), Tanaka
patent: 10-240629 (1998-09-01), None

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