Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-06-07
2005-06-07
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C703S002000
Reexamination Certificate
active
06904578
ABSTRACT:
A method for verifying a property associated with a target circuit is provided that includes receiving information associated with a target circuit, the information identifying a property within the target circuit to be verified. One or more partitioned ordered binary decision diagram (POBDD) operations are then executed using the information in order to generate a first set of states at a first depth associated with a sub-space within the target circuit. Bounded model checking may be executed using the first set of states in order to generate a second set of states at a second depth associated with the sub-space within the target circuit. The first set of states may be used as a basis for the second set of states such that the second depth is greater than the first depth.
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Iyer Subramanian K.
Jain Jawahar
Narayan Amit
Sahoo Debashis
Baker & Botts L.L.P.
Garbowski Leigh M.
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