System and method for verifying a layout of circuit traces...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000

Reexamination Certificate

active

10977823

ABSTRACT:
A system for verifying a layout of circuit traces on a motherboard includes a computer (1) and a database (2). The database is used for storing data generated and used by the system. The computer includes: a substandard layout area creating module (101) for creating substandard layout areas; a substandard segment data obtaining module (102) for obtaining from the database actual layout data on substandard segments placed in the substandard areas; a substandard length calculating module (103) for calculating a total length of all the substandard segments of a trace; and a satisfactory trace determining module (104) for comparing the total length of the substandard segments of the trace with a preset standard length for the trace, and determining whether the trace is satisfactory. A related method is also disclosed.

REFERENCES:
patent: 4641247 (1987-02-01), Laugesen et al.
patent: 4686629 (1987-08-01), Noto et al.
patent: 4815003 (1989-03-01), Putatunda et al.
patent: 4861272 (1989-08-01), Clark
patent: 5198986 (1993-03-01), Ikeda et al.
patent: 5404313 (1995-04-01), Shiohara et al.
patent: 5535134 (1996-07-01), Cohn et al.
patent: 5566079 (1996-10-01), Jun et al.
patent: 5600569 (1997-02-01), Nishiyama et al.
patent: 5831864 (1998-11-01), Raghunathan et al.
patent: 6067409 (2000-05-01), Scepanovic et al.
patent: 6122443 (2000-09-01), Nishikawa
patent: 6161056 (2000-12-01), Sato
patent: 6222739 (2001-04-01), Bhakta et al.
patent: 6223328 (2001-04-01), Ito et al.
patent: 6295634 (2001-09-01), Matsumoto
patent: 6327693 (2001-12-01), Cheng et al.
patent: 6493190 (2002-12-01), Coon
patent: 6560505 (2003-05-01), Kikuchi et al.
patent: 6581196 (2003-06-01), Eisenberg et al.
patent: 6643839 (2003-11-01), Nishio et al.
patent: 6665851 (2003-12-01), Donelly et al.
patent: 6988256 (2006-01-01), Teig et al.
patent: 7024419 (2006-04-01), Klenk et al.
patent: 7080343 (2006-07-01), Asai et al.
patent: 2001/0035799 (2001-11-01), Ueno et al.
patent: 2002/0010898 (2002-01-01), Sasaki et al.
patent: 2003/0167453 (2003-09-01), Smith et al.
patent: 2003/0212978 (2003-11-01), Asai et al.
patent: 2004/0040007 (2004-02-01), Harn
patent: 2004/0088670 (2004-05-01), Stevens et al.
patent: 2005/0170691 (2005-08-01), Mobley et al.
patent: 63204301 (1988-08-01), None
Watanabe et al., “A Hierarchical MCM Routing Using Four-Via Routing”, IEEE Asia Pacific Conference on Circuits and Systems, Nov. 18, 1996, pp. 389-392.

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