Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-10-23
2010-10-19
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07818700
ABSTRACT:
The invention relates to a method for verifying one or more exceptions in a logic circuit comprising the steps of: a first step of providing an initial representation of a logic circuit; a second step of indicating at least one exception for the logic circuit; a third step of introducing one or more potential malfunctions of the logic circuit related to the one or more exceptions into the representation of the logic circuit to produce a modified representation of the logic circuit; a fourth step of determining whether functional behavior of the modified representation of the logic circuit differs from functional behavior of the first representation of the logic circuit; and a fifth step of reporting a result relating to the difference in the functional behavior of the modified representation of the logic circuit from the functional behavior of the initial representation of the logic circuit.
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24IP Law Group
DeWitt Timothy R.
Kik Phallaka
Onespin Solutions GmbH
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