System and method for varying the starting conditions for a...

Details System and method for varying the starting conditions for a... System and method for varying the starting conditions for a...

2006-03-21

2009-12-01

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07627849

ABSTRACT:
A method for improving a resolution enhanced (RE) layout produced by an RE program that starts with a nominal integrated circuit layout. For at least one feature of said layout at least one critical feature quality is chosen from a set of feature qualities and at least one starting condition of said resolution enhancement program is adjusted in response to said at least one critical feature quality.

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patent: 2006/0095889 (2006-05-01), Cote et al.
P. Gupta, A. B. Kahng, C. H. Park, Detailed Placement for Improved Depth of Focus and CD Control, Proc. Asia and South Pacific Design Automation Conf,. Jan. 2005, pp. 343-348.
Puneet Gupta, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester, Selective Gate-Length Biasing for Cost-Effective Runtime Leakage Control, DAC 2004, Jun. 7-11, 2004, San Diego, California, USA.

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