Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2008-04-29
2008-04-29
Louis-Jacques, Jacques (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S745000
Reexamination Certificate
active
07366966
ABSTRACT:
A testing system includes a phase interpolator receiving a clock signal. An output of the phase interpolator is coupled to both a first signal distribution tree that includes a first delay line in each of its branches and a second signal distribution tree that includes a second delay line in each of its branches, thereby producing respective first and second delayed clock signals. A test signal generator generates a plurality of test signals that may simulate memory command or address signal. A multiplexer couples the test signals to first and second inputs of a transmitter in a normal test mode but to only the first input in a special test mode. The transmitter outputs the signal applied to its first input responsive to the first delayed clock signal and it outputs the signal applied to its second input responsive to the second delayed clock signal.
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Dorsey & Whitney LLP
Louis-Jacques Jacques
Micro)n Technology, Inc.
Nguyen Steve
LandOfFree
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