System and method for variable array architecture for memories

Details System and method for variable array architecture for memories System and method for variable array architecture for memories

2006-12-05

2006-12-05

Bataille, Pierre (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S167000

Reexamination Certificate

active

07146471

ABSTRACT:
A memory system that employs simultaneous activation of at least two dissimilar memory arrays, during a data manipulation, such as read or write operations is disclosed. An exemplary embodiment includes a memory system containing a plurality of arrays, each in communication with a common controller, wherein the arrays are activated by different supply voltage (Vdd). When a processor sends a command to retrieve or write data to the memory system, two or more arrays are addressed to supply the required data. By proper partitioning of the data between dissimilar arrays, the efficiency of data reading is improved.

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L. Benini, L. Macchiarulo, A. Macii, E. Macci, M. Poncino, “From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-Chip”, Jun. 2001, ACM, pp. 784-789.

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