Electrical computers and digital processing systems: support – Data processing protection using cryptography
Reexamination Certificate
2004-08-27
2008-10-28
Song, Hosuk (Department: 2135)
Electrical computers and digital processing systems: support
Data processing protection using cryptography
C713S193000, C713S181000
Reexamination Certificate
active
07444523
ABSTRACT:
A integrity control system uses the address bits to enable encryption and/or protection of data stored in a system memory. The encryption and protection mechanisms are coupled to the CPU by way of a data bus and to the memory by way of a data bus. An address bus that determines the location of data to be stored or retrieved from system memory has a plurality of address lines. At least one of the address lines enabling the encryption mechanism to encrypt data before storage in the memory and to decrypt data after retrieval from memory. Another address line enables the protection mechanism to generate a hash of the data. The hash is stored and used to determine whether data has been altered while stored in system memory.
REFERENCES:
patent: 3668651 (1972-06-01), Hornung
patent: 3742458 (1973-06-01), Inoue et al.
patent: 3827029 (1974-07-01), Schlotterer et al.
patent: 3829840 (1974-08-01), Burk et al.
patent: 4476524 (1984-10-01), Brown et al.
patent: 4740916 (1988-04-01), Martin
patent: 4771458 (1988-09-01), Citta et al.
patent: 5058164 (1991-10-01), Elmer et al.
patent: 5081675 (1992-01-01), Kittirutsunetorn
patent: 5224166 (1993-06-01), Hartman, Jr.
patent: 5233616 (1993-08-01), Callander
patent: 5347428 (1994-09-01), Carson et al.
patent: 5421006 (1995-05-01), Jablon et al.
patent: 5426750 (1995-06-01), Becker et al.
patent: 5634108 (1997-05-01), Freeman
patent: 5652793 (1997-07-01), Priem et al.
patent: 5825878 (1998-10-01), Takahashi et al.
patent: 5944821 (1999-08-01), Angelo
patent: 6026293 (2000-02-01), Osborn
patent: 6151618 (2000-11-01), Wahbe et al.
patent: 6195752 (2001-02-01), Pfab
patent: 6199163 (2001-03-01), Dumas et al.
patent: 6292892 (2001-09-01), Davis
patent: 6633963 (2003-10-01), Ellison et al.
patent: 6651171 (2003-11-01), England et al.
patent: 6704871 (2004-03-01), Kaplan et al.
patent: 6735673 (2004-05-01), Kever
patent: 6745307 (2004-06-01), McKee
patent: 6778667 (2004-08-01), Bakhle et al.
patent: 6934817 (2005-08-01), Ellison et al.
patent: 7107459 (2006-09-01), Caronni et al.
patent: 7111146 (2006-09-01), Anvin
patent: 7117373 (2006-10-01), Trimberger et al.
patent: 7124274 (2006-10-01), Watt et al.
patent: 7124302 (2006-10-01), Ginter et al.
patent: 7313705 (2007-12-01), Turkboylari
patent: 2002/0007456 (2002-01-01), Peinado et al.
patent: 2002/0016846 (2002-02-01), Ono
patent: 2002/0147918 (2002-10-01), Osthoff et al.
patent: 2002/0150243 (2002-10-01), Craft et al.
patent: 2003/0074567 (2003-04-01), Charbonneau
patent: 2003/0101322 (2003-05-01), Gardner
patent: 2003/0133574 (2003-07-01), Caronni et al.
patent: 2003/0140245 (2003-07-01), Dahan et al.
patent: 2003/0188178 (2003-10-01), Strongin et al.
patent: 2003/0200448 (2003-10-01), Foster et al.
patent: 2003/0204693 (2003-10-01), Moran et al.
patent: 2004/0151319 (2004-08-01), Proudler
patent: 2007/0014412 (2007-01-01), Rolliins
patent: 2007/0136543 (2007-06-01), Ehama et al.
patent: 0 186 230 (1986-07-01), None
patent: 0 908 810 (1999-04-01), None
patent: WO 98/36517 (1998-08-01), None
patent: WO 00/26791 (2000-05-01), None
“Computer Memory,” http:/
cca.bournemouth.ac.uk/CourseInfo/BAVisAn/Year1/CompSys/Memory/, Jan. 18, 1996, 4 pages.
“Address Decode—General IO,” http://www.onastick.clara.co.uk/address.htm, 1992, 6 pages.
Black, J. et al., “UMAC: Fast and Secure Message Authentication,”Advances in Cryptology—CRYPTO '99, Lecture Notes in Computer Science, Wiener, M. (ed.), 1999, vol. 1666, 18 pages.
Engler, D. et al., “The Operatiing System Kernel as a Secure Programmable Machine,”Proceedings of the 6thWorkshop on ACM SIGOPS European Workshop: Matching Operating Systems to Application Needs, Wardern, Germany, 1994, 62-67.
Halevi, S. et al., “A Tweakable Enciphering Mode,”Advances in Cryptology—CRYPTO '03, Lecture Notes in Computer Science, Boneh, D. (ed.), 2003, vol. 2729, 33 pages.
Jutla, C.S., “Encryption Modes with Almost Free Message Integrity,”Proceedings of the International Conference on the Theory and Application of Cryptographic Techniuqes: Advances in Cryptology, 2001, 15 pages.
Kirovski, D. et al., “Enabling Trusted Software Integrity,”Proceedings of the 10thInternational Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, California, 2002, 108-120.
Lie, D. et al., “Implementing an Untrusted Operation System on Trusted Hardware,”Proceedings of the 19thACM Symposium on Operating Systems Principles, Bolton Landing, New York, 2003, 178-192.
Lie, D. et al., “Architectural Support for Copy and Tamper Resistant Software,”ACM SIGPLAN Notices, 2000, 35(11), 8 pages.
Schroeder, M.D. et al., “A Hardware Architecture for Implementing Protection Rings,”Communications of the ACM, Mar. 1972, 15(3), 157-170.
Suh, G.E. et al., “AEGIS: Architecture for Tamper-Evident and Tamper-Resistant Processing,”Proceedings of the ICS, San Francisco, California, 2003, 160-171.
Suh, G.E. et al., “Hardware Mechanisms for Memory Integrity Checking,” 2002, 18 pages.
Suh, G. E. et al., “Efficient Memory Integrity Verification and Encryption for Secure Processors,”Proceedings of the 36thInternational Symposium on Microarchitecture, 2003, 1-12.
Wetzel, J. et al., “PowerPC Operating Environment Architecture,” Dec. 2003,Book III, Version 2.01, Table of Contents and pp. 1-119.
Wu, M. et al., “Improving TLB Miss Handling with Page Table Pointer Caches,” Dec. 1997, 10 pages.
Zachary, J. et al., “Bidirectional Mobile Code Trust Management Using Tamper Resistant Hardware,”Mobile Networks and Applications, 2003,8, 137-143.
Gay, C., “M68000 Family Memory Management-Part 2,”Electronic Engineering, Morgan-Grampian Ltd., London, 1986, 59-68.
Suh et al., “AEGIS: Architecture for Tamper-Evident and Tamper-Resistant Processing,” 2003, ACM 1-58113-733-8/03/0006.
Intel Communications, “Intel 186/386/486 Processors,” 2002, Order No. 251397-001.
Nevelsteen et al., “Software Performance of Universal Hash Functions,” 1999, EUROCRYPT, LNCS 1592, pp. 24-41.
United States Patent and Trademark Office: Non-Final Office Action dated Jun. 27, 2006, U.S. Appl. No. 7,356,668 issued Apr. 8, 2008, 14 pages.
United States Patent and Trademark Office: Non-Final Office Action dated Jan. 10, 2008, U.S. Appl. No. 10/927,729, dated Aug. 27, 2004, 9 pages.
United States Patent and Trademark Office: Non-Final Office Action dated Sep. 11, 2006, U.S. Appl. No. 10/928,786 dated Aug. 27, 2004,10 pages.
United States Patent and Trademark Office: Non-Final Office Action dated Sep. 10, 2006, U.S. Appl. No. 10/928,786 dated Aug. 27, 2004,10 pages.
United States Patent Trademark Office: Non-Final Office Action dated Apr. 30, 2008, U.S. Appl. No. 10/928,786 dated Aug. 27, 2004, 9 pages.
United States Patent and Trademark Office: Final Office Action dated Dec. 7, 2006, U.S. Appl. No. 7,356.668 issued Apr. 8, 2008, 13 pages.
United States Patent and Trademark Office: Non-Final Office Action dated Mar. 27, 2008, U.S. Appl. No. 10/929,036 dated Aug. 27, 2007, 10 pages.
Andrews Jeffrey A.
Morais Dinarte R.
Microsoft Corporation
Song Hosuk
Woodcock & Washburn LLP
LandOfFree
System and method for using address bits to signal security... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for using address bits to signal security..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for using address bits to signal security... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4017871