System and method for translation of SDRAM and DDR signals

Details System and method for translation of SDRAM and DDR signals System and method for translation of SDRAM and DDR signals

2002-03-12

2004-03-16

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S219000, C365S233100, C365S238500

Reexamination Certificate

active

06707756

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates generally to memory systems and more particularly to a system and method for translating signals between SDRAM and DDR memory systems.
2. Status of the Prior Art
Synchronous Dynamic Random Access Memory (SDRAM) is a type of computer memory that runs synchronously to the system clock. SDRAM is tied to the system clock and is designed to be able to read or write from memory in a burst mode after a prescribed latency period (i.e., typically after an initial read or write latency). SDRAM can write from memory at 1 clock cycle per access (zero wait states) at memory burst speed up to 133 MHZ or SDRAM can read from memory at 2 clock/3 clock cycles per access at memory burst speeds up to 133 MHZ or higher. For instance, memory is written or read from the SDRAM on the positive edge of the clock signal. Accordingly, data is only transferred once per clock cycle.
SDRAM memory has become a memory standard for modern personal computers (PC's) because its synchronized design permits support for high bus speeds. For proper operation, the entire memory must be fast enough for the bus speed of the system. Due to the increased speed of the SDRAM, it has become one of the leading standards for computer memories.
Recently, a new type of memory system has been created which has data read/write times faster than standard SDRAM memory. The new type of memory is call Double Data Rate (DDR) SDRAM. The significant difference between SDRAM and DDR SDRAM is that data is written and read on both edges of the clock signal. For instance, data can be accessed on both the positive and negative edges thereby increasing the bandwidth of the memory by two.
EXAMPLE
System Clock 100 MHZ
SDRAM
100 MHZ×72 Bit (8 Byte+1 Byte
ECC
)=800 MB/Second Transfer Rate
DDR SDRAM
200 MHZ×72 Bit (8 Byte+1 Byte
ECC
)=1600 MB/Second Transfer Rate
The bandwidth of the DDR SDRAM system is increased because data can be accessed on both edges (i.e. positive and negative) of the system clock thereby doubling the speed of the system. Furthermore, in a DDR SDRAM system, the data is written/read with a Data Strobe (DQS) signal which is an asynchronous signal.
Both DDR SDRAM and regular SDRAM memory are not interchangeable. Accordingly, a system designed for DDR SDRAM cannot use regular SDRAM memory. Conversely, a system designed for regular SDRAM memory cannot be upgraded to DDR SDRAM by simply inserting the DDR SDRAM memory. This may be inconvenient for owner's and manufacturers of PC's because they might already have a large stockpile of only one type of memory. For instance, a manufacturer of PC's might have a large stock of regular SDRAM memory that needs to be used. However, the PC's are designed for DDR SDRAM memory. The stock of regular SDRAM memory cannot be used in the PC's due to incompatibility such that the regular SDRAM memory will be wasted.
The present invention addresses the above-mentioned deficiencies in the different memory systems by providing a translator that can make systems designed for one type of memory compatible with the other type of memory. More specifically, the present invention provides a method and system for allowing regular SDRAM memory to be used by a system designed for DDR SDRAM memory. Conversely, the present invention allows systems designed for DDR SDRAM memory to use regular SDRAM memory. Accordingly, the present invention provides a translator which allows either type of memory (i.e, DDR SDRAM or regular SDRAM) to be used.
BRIEF SUMMARY OF THE INVENTION
A circuit for converting signals between a memory interface and a memory array is disclosed. The memory interface is not the same type as the memory array such that the signals between the interface and the array need to be synchronized and translated. The circuit includes an interface converter for shifting the logic levels of the signals between the memory interface and the memory array. Furthermore, the circuit has a translation block for translating and synchronizing the signals. In this respect signals between the memory array and the memory interface are synchronized and translated such that the memory array can be used with a memory interface of a different type.
In accordance with the present invention, the memory interface is a SDRAM memory interface and the memory array is an DDR SDRAM memory array. Alternatively, the memory interface may be a DDR SDRAM memory interface and the memory array is a SDRAM memory array. In either instance, the interface converter will be configured to shift the logic levels between the memory interface and the memory array between LVTTL and SSTL-II logic levels. Furthermore, the translation block will include a burst address decoder for decoding burst address lengths between the memory interface and the memory array. The translation block further includes a buffer for synchronizing the signals between the memory interface and the memory array due to any bandwidth mismatch.
In accordance with the present invention, there is provided a method of synchronizing and translating signals between a memory array and a memory interface wherein the memory array is not the same type as the memory interface. The method commences by shifting the logic levels of the signals between the memory array and the memory interface. In this respect, the logic levels of the signals are shifted between LVTTL and SSTL-II logic levels for SDRAM and DDR SDRAM conversion. Next, address and control signals are translated between the memory interface and the memory array. Finally, the signals are synchronized between the memory array and the memory interface. The synchronization process allows for bandwidth mismatch between the memory array and the memory interface. Typically, the signals are translated using a burst address decoder and synchronized through the use of a buffer.


REFERENCES:
patent: 6392946 (2002-05-01), Wu et al.
patent: 6501671 (2002-12-01), Konishi
patent: 6507888 (2003-01-01), Wu et al.

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