Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate
1998-06-03
2001-05-22
Eng, David Y. (Department: 2155)
Electrical computers and digital processing systems: processing
Processing control
Branching
Reexamination Certificate
active
06237088
ABSTRACT:
CROSS-REFERENCES TO RELATED APPLICATIONS
The named inventor of the present application has a co-pending United States patent applications entitled “Apparatus and Method for Detecting and Handling Self-Modifying Code Conflicts in an Instruction Fetch Pipeline” (Application No. 09/088,634 filed Jun. 2, 1998). This application is hereby incorporated by reference in its entirety. This application is owned by the same assignee of the present Application.
BACKGROUND
1. Field
The present invention relates to the field of electronics. More specifically, the invention relates to an apparatus, system and method for tracking in-flight instructions in a pipeline.
2. General Background
Prior generation microprocessors feature circuitry arranged to successively fetch and execute instructions. More specifically, this circuitry fetches instruction pointers (IPs) and places these IPs in an instruction pipeline. The “instruction pipeline” generally includes a plurality of processing stages, wherein the first few processing stages are referred to as a “front-end pipeline” and the remaining processing stages are referred to as a “back-end pipeline”. Since IPs are loaded into the front-end pipeline and instructions associated with these IPs are subsequently executed at the back-end pipeline, in-flight IPs are subject to self-modifying code (SMC) conflicts.
A “SMC conflict” is a condition where the execution of an instruction of an executable program causes self-modification of that executable program. This self-modification may lead to the execution of “stale” instruction data already progressing through an instruction pipeline. In particular, a SMC conflict may occur for a number of reasons including, for example, those instances when a new instruction is created or when data embedded into an instruction of a repeatedly executable program is modified. Thus, various SMC handling techniques have been adopted over the years.
For example, earlier generation processors, such as i80486™ and PENTIUM® microprocessors produced by Intel Corporation of Santa Clara, Calif., snooped the instruction pipeline for SMC conflicts. This technique is suitable for pipelines having a small number of processing stages and supporting in-order instruction processing. However, these early generation processors are unable to track out-of-order pipelining of instructions.
Another technique, utilized by the PENTIUM® PRO microprocessor, requires the use of an instruction victim cache (IVC) in combination with a normal instruction cache (I-cache) to guarantee that all of the instructions in the pipeline would be resident in one of these caches. However, this cache architecture requires complicated management logic.
Hence, it would be advantageous to provide a system and method to track in-flight instructions in which the resultant information can be used to detect SMC conflicts for example.
SUMMARY
In one embodiment, for example, the invention comprises a line address buffer and companion logic. The line address buffer contains a first plurality of line addresses. Each line address is associated with a fetched instruction pointer. The comparison logic compares a second plurality of line addresses with a target address of an instruction being executed in order to detect an event.
REFERENCES:
patent: 5265213 (1993-11-01), Welser et al.
patent: 5692167 (1997-11-01), Grodhowski et al.
patent: 5835949 (1998-11-01), Quattromani et al.
patent: 5867701 (1999-02-01), Brown et al.
Blakely , Sokoloff, Taylor & Zafman LLP
Eng David Y.
Intel Corporation
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