Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing
Reexamination Certificate
2000-12-11
2004-11-09
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Direct memory accessing
C710S022000, C710S023000, C710S033000, C710S036000, C710S107000, C709S200000, C709S212000, C711S100000
Reexamination Certificate
active
06816924
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to data communication systems and, in particular, to an improved trace and debug system and, particularly, to an improved system for a direct memory access (DMA) handler for an Internet Protocol (IP) over asynchronous transfer mode (ATM) system.
2. Description of the Related Art
The Internet Protocol (IP) is one of the most popular networking protocols in use today. Briefly, IP encapsulates data into packets or frames of varying length. However, IP does not provide true quality of service (QoS), which is a requirement of multimedia messaging. Asynchronous transfer mode (ATM) systems pack data into equal length cells and also provide for true QoS.
Systems that employ IP over ATM must therefore provide for handling of the varying length IP frames and the fixed length ATM cells without doing violence to the ATM QoS requirements. One approach is to receive the IP frames, disassemble them, and reassemble them as ATM cells. This does not necessarily provide an optimal result, however. As such, there is a need for an improved system for handling IP frames and ATM cells.
Further, as can be appreciated, such systems are relatively complex and, as such, it is desirable to provide on-chip trace and debug support.
SUMMARY OF THE INVENTION
These and other drawbacks in the prior art are overcome in large part by a direct memory access device (DMA) in accordance with the present requesters over a shared media by interleaving frames and cells.
A DMA controller according to an implementation of the present invention includes a bus driver, a bus sniffer, a priority controller and a context machine. The bus sniffer is used to identify a cast type of a transfer on the bus, i.e., whether the transfer is a frame or cell transfer. The priority controller asserts a signal allowing access to the bus. The context machine stores system context. The controller supervises interleaving of frames and cells on the bus and asserts a frame end signal when a frame has been transmitted.
A trace and debug support unit is also provided, that works in conjunction with the bus sniffer. The trace and debug support unit maintains in memory one or more configurable filter rules which are used to define parameters of the trace history.
According to one implementation of the invention, a plurality of conditions or rules are provided, satisfaction of one or more of which causes a trace history to be filed. For example, a transfer-specific signal may be issued, whereby all cells of the identified transfer are filed as part of the trace history. Alternatively, a connection-specific flag may be carried with each cell, whereby all cells of the specific connection are filed as part of the trace history.
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Casiano Angel L
Fish & Richardson P.C.
Gaffin Jeffrey
Infineon Technologies North America Corp.
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