System and method for topology selection to minimize leakage...

Details System and method for topology selection to minimize leakage... System and method for topology selection to minimize leakage...

2006-08-29

2006-08-29

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07100144

ABSTRACT:
A system for topology selection to minimize leakage power during synthesis, wherein the system is configured to receive a circuit model that has one or more circuit gates. The system is further configured to receive a library having one or more logic gates, wherein each logic gate has a topology and the leakage sensitivities for each of the topologies is calculated. The system is then configured to synthesize a new circuit model by selecting one or more of the topologies based on its leakage sensitivities, wherein the new circuit model has reduced current leakage.

REFERENCES:
patent: 6345379 (2002-02-01), Khouja et al.
patent: 2002/0144223 (2002-10-01), Usami et al.
patent: 2003/0126579 (2003-07-01), Whitaker et al.
patent: 2005/0044515 (2005-02-01), Acar et al.

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