Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-04-05
2005-04-05
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06877143
ABSTRACT:
A computer-implemented method abstracts the timing constraints for latches internal to a digital logic circuit, resulting in a clock characterization model. Timing information (such as propagation delays, set-up and hold requirements) for latches and combinational logic circuits contained in a digital logic circuit are received, as is a description of a class of clock scheme for clocking the circuit. Clock parameters are selected for the clock scheme class. The internal timing constraints for the digital logic circuit are expressed as timing constraint expressions which are a function of the clock parameters. The expressions are combined to define a region of feasible clock operation expressed in terms of the clock parameters.
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Mortazavi Mohammad
Palermo Robert J
Sakallah Karem A.
Venkatesh Shekaripuram V.
Bingham & McCutchen LLP
Cadence Design Systems Inc.
Garbowski Leigh M.
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