Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2007-01-19
2010-10-12
Beausoliel, Robert (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
Reexamination Certificate
active
07814374
ABSTRACT:
A multiprocessor chip system having the capability to capture and preserve intermediate machine error state data, wherein the system comprises a second level cache, wherein the second level cache is commonly interfaced with a primary and secondary processing core, and at least two primary error event registers, wherein each primary error event register is logically associated to a respective processing core. Further, at least two secondary error event registers, wherein each secondary error event register is logically associated to a respective processing core, and at least two sub-primary error accumulation registers, wherein each sub-primary error accumulation register is logically associated to a respective primary error event register and a secondary error event register.
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Balazich Douglas
Billeci Michael
Saporito Anthony
Slegel Timothy J.
Beausoliel Robert
Campbell John
Cantor & Colburn LLP
International Business Machines - Corporation
Riad Amine
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