Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2007-10-16
2007-10-16
Tu, Christine T. (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S798000, C714S735000
Reexamination Certificate
active
11298163
ABSTRACT:
Write strobe preamble/postamble test circuitry includes a test signal generator generating first and second digital signals. Also included are a pair of phase interpolators for varying the transition times of respective transmitter clock signals. When enabled, a transmitter uses the transmitter clock signals to transmit a write data strobe signal corresponding to the first and second digital signals to memory devices being tested. The transmitter is enabled by an enable signal generated by a third phase interpolator. By varying the timing of the enable signal, the third phase interpolator can vary the duration of preambles and postambles of respective write data strobe signals.
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LaBerge Paul A.
Lunzer Keith J.
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Tu Christine T.
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