Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2003-04-01
2004-08-10
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S189020
Reexamination Certificate
active
06775193
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to the testing of semiconductor memory devices, such as static random access memory (“SRAM”) devices. More particularly, the present invention relates to a system and method for testing multiple embedded memories within an integrated circuit.
BACKGROUND OF THE INVENTION
Testing of semiconductor memory devices is an important step in semiconductor fabrication processes. Integrated circuits and the chips housing these circuits may include multiple embedded memory devices or modules. Each memory cell within an embedded memory must be tested to determine whether it is functioning properly. That is, each memory cell must be tested to ensure that data can properly be written to and read from the memory cell. If even one memory cell in a memory device is defective, the memory device and integrated circuit may not function properly.
Semiconductor fabrication processes typically employ external testing circuits, which may be coupled to an integrated circuit by probing a chip pad. Once attached, a testing circuit will run a program to test a memory device on the circuit. For example, the testing circuit and program may operate to write a series of binary values (e.g., low or “0” values and high or “1” values) to the cells of the memory device, read the values stored in the cells, and compare the values to the correct or expected values to ensure proper operation of each memory cell. The programs employed by the testing circuits are tailored to the specific size, density and configuration of the memory device being tested. For instance, the program will typically correspond to the number of cells in each row and column of the memory device. Therefore, different programs are required to test different types of memory devices. As a result, each time a memory device having a different density or configuration is tested, the testing circuit is disconnected from the integrated circuit to load a new testing program. Once the new testing program is loaded, the testing circuit is reconnected by probing the integrated circuit, and the new memory device may then tested. Because of the increasing density and complexity of today's integrated circuits, the above-described, conventional system and method for testing memories suffers from several significant drawbacks.
Due to developments in semiconductor processing, integrated circuits have increased in size and complexity, and the number and types of memory modules that may be formed on a chip has grown substantially. Integrated circuits have been developed that include over 50 different embedded memory modules. Since the memory modules often differ in density and configuration, many different programs must be run in order to test each memory module. This creates several problems. For example, reloading different testing programs is performed at the end of a batch and is very time consuming. Having to load many different programs significantly increases the overall processing time and decreases efficiency. Furthermore, repeatedly probing the chip pads damages the wafers. The number over times each wafer can be probed without causing unacceptable damage is limited. Thus, probing wafers many times to run different testing programs may result in a significantly reduced yield.
There is therefore a need for an improved system and method for testing embedded memories, which overcomes the foregoing drawbacks of prior memory systems and which allows for testing of integrated circuits having many different memory modules of varying density and configuration.
SUMMARY OF THE INVENTION
The present invention provides a system and method for testing embedded memories. In one embodiment, the present invention logically combines many different embedded memories into one or more large, virtual memory blocks in order to test multiple memories together. The invention expands and/or defines the X and/or Y address space in all memories in order to cover all memories combined. Compare circuits associated with each memory module are used to compare the data output from each memory cell to an expected value (e.g., to a value that would be expected if the memory cell was operating properly). The invention further uses mask logic to “mask out” any unimplemented address space in each individual memory. The mask logic will always indicate that the comparison or memory test passed when unimplemented addresses are selected. The results of the comparison may be bundled and multiplexed to a test input/output port.
One advantage of the present invention is that it utilizes addressing to allow multiple embedded memories to be tested as a virtual memory block, independent of the actual physical location or configuration of the memories.
Another advantage of the present invention is that it allows multiple embedded memories to be tested on a chip without having to repeatedly probe the chip, thereby preventing damage to the chip and increasing overall yield.
Another advantage of the present invention is that allows multiple memories to be tested on a chip without having to load many different programs, thereby significantly reducing processing time and increasing efficiency.
According to a first aspect of the present invention, a system for testing a plurality of embedded memory modules on a chip is provided. The system includes a plurality of embedded memories that are grouped into one or more virtual memory blocks, each of the embedded memories including a plurality of memory cells, which are each assigned an associated address within the one or more virtual memory blocks; a test controller that is adapted to be coupled to the plurality of embedded memories, to communicate test data to the memory cells that are associated with assigned addresses, and to read data from the memory cells; and at least one compare circuit for comparing the data read from the memory cells to expected data, in order to determine if each of the memory cells is operating properly.
According to a second aspect of the present invention, a method is provided for testing a plurality of memory modules embedded on a chip. The method includes the steps of: defining an address space of the chip to cover the plurality of memory modules combined; and testing the plurality of memory modules as a single virtual memory block.
According to a third aspect of the present invention, a method of testing a plurality of embedded memories on a chip is provided. The method includes the steps of: arranging the plurality of embedded memories into one or more virtual memory blocks; assigning addresses to cells of the embedded memories corresponding to the location of the embedded memories within the one or more virtual memory blocks; and testing each of addresses of the one or more virtual memory blocks in a predetermined sequence, effective to test each of the corresponding cells of the embedded memories.
These and other features, advantages, and objects of the invention will become apparent by reference to the following specification and by reference to the following drawings.
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Shu Lee-Lean
Shyu Taiching
Giga Semiconductor, Inc.
Gray Cary Ware & Freidenrich LLP
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