System and method for testing memory arrays

Details System and method for testing memory arrays System and method for testing memory arrays

2005-12-20

2005-12-20

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

Reexamination Certificate

active

06978406

ABSTRACT:
A memory array test system and method provides for testing a memory array in a manufactured chip. In accordance with one aspect of the invention, a system includes memory test input logic that acquires test data via a data port, a memory test enable logic and a memory test output logic. In accordance with another aspect of the invention, a method acquires test data via a data port, writes the test data to a memory address in the memory array, and reads output data from the memory address in the memory array. Then, the method compares the test data and the output data to determine if the memory address in the memory array passes a test.

REFERENCES:
patent: 6550023 (2003-04-01), Brauch et al.
patent: 6574762 (2003-06-01), Karimi et al.
patent: 6643807 (2003-11-01), Heaslip et al.
patent: 6769081 (2004-07-01), Parulkar

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