Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1999-07-26
2004-02-17
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S727000, C714S730000
Reexamination Certificate
active
06694461
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to the testing of integrated memories, and more specifically to the testing of memories having test collars.
BACKGROUND OF THE INVENTION
The testing of complex integrated devices, such as microprocessors, is necessary in order to assure proper operation of these devices. For integrated devices that have associated memory blocks, it is necessary to assure functionality of the memory. One prior art method of testing integrated memory blocks is to pin-out, either directly or through multiplexors, the address, control and data pins of the memory. In this manner, it is possible to exercise all storage locations of the memory to ensure proper operation. However, the pin count needed to test a device in this manner can be larger than the number of pins available. In addition, for each memory multiplexed in this manner, additional logic is introduced into the delay paths of the device, resulting in slower input/output (IO) propagation times that can affect performance.
Prior art
FIG. 1
illustrates another prior art solution for testing integrated memories. Specifically, a Built-In Self Test (BIST) controller is used to automatically verify functionality of individual blocks of memory. For example, on start up, the BIST controller will perform a test routine to verify the integrity of the memory. If errors are found, they are reported.
FIG. 1
illustrates a device
100
having two BIST controllers for testing three integrated memories. The portion
100
of
FIG. 1
represents a single block of memory being tested by a BIST controller. Generally, the BIST controller includes a test collar which, in conjunction with the BIST controller, generates addresses, data values, and compares received results to expected results. The portion
120
of
FIG. 1
represents a double block of memories being tested by a single BIST controller. The use of BIST technology dedicates BIST hardware to specific memory locations. As a result, when a device has many different sizes or kinds of memory devices it is necessary for separate BIST controllers and associated collars to be provided. This increases the size of a memory block in the range of 2% to 8%.
Testability techniques can be implemented using modem simulation and layout tools. However, these tools only perform fixed test algorithms. For example, these tools are only capable of implementing March algorithms to detect errors. March algorithms read and write data in an up direction (incrementing address values) or in a down direction. While such tests are good enough for establishing production testing of traditional sized memories, sufficient test coverage is not available for development and debugging purposes.
Conventionally available tools and techniques for testing integrated memories do not have the flexibility to test wide varieties of memories. For example, modem graphics devices utilize small word sizes (8-bits or less) and very large word sizes (128-bits or more). Within these ranges, the address space can be a few bytes or Kilobytes. However, a problem with commercially available tools is that they are optimized to efficiently support only the most common memory types and sizes.
Therefore, a system and method for testing integrated memories that overcomes these problems would be desirable.
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ATI International Srl
De'cady Albert
Torres Joseph D.
Vedder Price Kaufman & Kammholz P.C.
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