System and method for testing abstracted timing models

Details System and method for testing abstracted timing models System and method for testing abstracted timing models

2002-01-30

2004-07-13

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06763507

ABSTRACT:

FIELD OF THE INVENTION
The present invention is directed to a system for testing integrated circuit designs and more particualrly, to a system for determining whether the deviation between a timing value for an extracted model representation of a circuit design falls within a permissible range from a timing value for a static model of the same circuit design.
BACKGROUND
In the design of integrated circuits, static timing tools such as Prime Time® by Synopsys® are commonly used to evaluate static timing models of a circuit prior to actual fabrication of the circuit in semiconductor material. As a part of pre-fabrication evaluation of a circuit design, a timing value for a static timing model representation of the circuit is determined and subsequently a timing value for an extracted model of the same circuit is determined. These timing values are then manually evaluated to determine whether or not the timing value of the extracted model falls within a predetermined range of the timing value for the static model of the circuit.
As a typical integrated circuit design incorporates tens of thousands to millions of gates and wiring traces, the process of analyzing an integrated circuit design using these typical techniques can be very time consuming as each signal path of the circuitry must be modeled and evaluated. Further, a great deal of manual intervention is required to compare the timing values and operation of the extracted timing model with the timing value and operation of the static timing model to determine whether or not the circuit design is successful
SUMMARY OF THE INVENTION
Other features and advantages of the present invention will become apparent from the following description, drawings and claims. The present invention provides a system and method for testing abstracted timing models. Briefly described, in architecture, one embodiment of the system, among others, can be implemented as follows.
A controller is provided that is configured by software instructions stored on memory. This controller is configured to receive a static model timing value and to receive an extracted model timing value. The controller is further configured to determine the difference between the static model timing value and the extracted model timing value and then to determine whether the difference is within a predetermined permissible range. If so, the controller outputs an indication of success if said difference falls within said predetermined permissible range.
The present invention can also be viewed as providing methods for testing abstracted timing models. In this regard, one embodiment of such a method, among others, can be broadly summarized by the following steps: receiving a static model timing value. Receiving an extracted model timing value and determining the difference between the static model timing value and the extracted model timing value. A determination is made as to whether the difference is within a predetermined permissible range. If the difference does fall within the predetermined permissible range, an indication of success/qualification is output.
Other systems, methods, features, and advantages of the present invention will be or become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of the present invention, and be protected by the accompanying claims.


REFERENCES:
patent: 6360356 (2002-03-01), Eng
patent: 6438731 (2002-08-01), Segal
patent: 6487705 (2002-11-01), Roethig et al.
patent: 2003/0121013 (2003-06-01), Moon et al.
Schimpfle et al., “High-Level Circuit Modeling for Power Estimation,” IEEE, 1999, pp. 807-810.*
M. R. Frerichs, “Precise Extraction of Ultra Deep Submission Interconnect Parasitic with Parameterized 3D-Modeling,” IEEE, Feb. 2, 2001, pp. 50-55.

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