System and method for testing a memory

Details System and method for testing a memory System and method for testing a memory

2006-04-18

2006-04-18

Nghiem, Michael (Department: 2863)

Data processing: measuring, calibrating, or testing

Testing system

Of circuit

Reexamination Certificate

active

07031866

ABSTRACT:
A method and apparatus for testing a memory at speed. A test and repair wrapper integrated with a memory instance is operable to receive test information scanned in from a built-in self-test and repair (BISTR) processor. Logic circuitry associated with the test and repair wrapper is operable to generate address, data and command signals based on the scanned test information, wherein the signals are used for effectuating one or more tests with respect to the memory instance.

REFERENCES:
patent: 6396760 (2002-05-01), Behera et al.
patent: 6519202 (2003-02-01), Shubat et al.
patent: 6587979 (2003-07-01), Kraus et al.
patent: 6691264 (2004-02-01), Huang
patent: 2005/0028050 (2005-02-01), Ganry

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