System and method for testing a clock signal

Details System and method for testing a clock signal System and method for testing a clock signal

1996-06-14

2001-10-30

Le, Dieu-Minh (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S814000

Reexamination Certificate

active

06311295

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates in general to data processing systems, and in particular, to a system and method for detecting phase misalignment of on-chip generated clock signals.
BACKGROUND OF THE INVENTION
The system clock is the electronic circuit in a computer that generates a steady stream of tiny pulses—the digital signals that synchronize every operation. The system clock signal typically operates at a specific frequency between 50 million and 150 million cycles per second (megahertz, or MH) and is precisely set by a quartz signal inside the clock circuit The clock rate of a computer is one of the prime determinants of its overall processing speed, and it can go as high as the other components of the computer allow.
In order to achieve high performance, modern microprocessors often generate or synthesize on-chip clocking by multiplying the frequency of an off-chip source. Thus, a 50 MHz off-chip source can be used to generate on-chip clocking of 200 MHz for instance. The clock generation and distribution logic in a high performance microprocessor is sensitive and complex involving complex analog circuits, delay lines and feedback circuits, which are very sensitive to manufacturing process variations.
During manufacturing, and the debug and system testing, it is not practical to directly observe the on-chip clocking. Techniques to check the on-chip clocking during manufacturing are complex and time consuming and do not easily fit into the process of checking the digital circuitry. In order to reduce the test time for chips and to improve the quality of the testing of the clocking circuitry, a low cost but effective test is needed.
SUMMARY OF THE INVENTION
The foregoing need is solved by the present invention, which utilizes a test circuit for receiving a reference clock signal and a sense clock signal and subsequently determining whether or not the reference and sense clock signals are either correct multiples of each other and/or in phase with each other. The test circuit may be located on the same chip with the microprocessor and the clock circuitry. The clock circuitry may include a phase locked loop (“PLL”) circuit for receiving the reference clock signal and producing a sense clock signal for use by the remainder of the chip, wherein the sense clock signal is a multiple of the reference clock signal.
The test circuit may count the number of cycles of the sense clock signal occurring within a predetermined amount of time, which may be proportional to the reference clock period. Alternatively, the sense clock signal and the reference clock signals may be passed through an XOR circuit and then the number of cycles counted within a predetermined time period. In both cases, if the number of cycles counted is not what was expected, then it is known that the sense clock signal was not properly produced by the PLL circuit.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.


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