Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2005-04-19
2005-04-19
Beausoliel, Robert (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S029000, C714S030000, C714S035000, C714S037000, C324S763010, C324S764010, C324S765010
Reexamination Certificate
active
06883113
ABSTRACT:
A procedure for temporally isolating an environmentally dependent integrated circuit fault includes the steps of determining a marginally failing and a minimally passing environmental condition corresponding to the fault; identifying a clock cycle Tmaxat which the fault was first detected; determining a candidate clock cycle at which the fault may have occurred; and iteratively a) applying test pattern subsets from an initial clock cycle through the candidate clock cycle under the marginally failing environmental condition; b) applying remaining test patterns under the minimally passing environmental condition; and c) adjusting the candidate clock cycle based upon whether the fault occurred during test pattern subset application up through the candidate clock cycle under the marginally failing environmental condition. Candidate clock cycle adjustment in accordance with a binary search technique enables determination of an exact clock cycle at which the fault occurred in a maximum of Log2(Tmax+1) iterations.
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McWilliam Bruce
Storey Thomas M.
Todd Ronald
Bae Systems Information and Electronic Systems Integration Inc.
Beausoliel Robert
Graybeal Jackson Haley LLP
Long Daniel J.
Puente Emerson
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