Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
1999-03-31
2002-09-17
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S400000, C712S223000, C712S244000, C712S245000
Reexamination Certificate
active
06453424
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to computer processors and, more particularly, to temporally controlling the execution of instructions in a microprocessor or digital signal processor.
2. Background Description
So-called superscalar Microprocessors and Digital Signal Processors operate by sequentially executing instructions which specify the individual operations. These sequential operations can include, for example, adding two numbers, subtracting numbers, multiplying numbers, moving data, performing boolean math, etc. A typical program for a microprocessor is, basically, a sequence of instructions written to perform a particular task.
Some program instructions may reorder instruction execution sequence on the fly. For example, a short sequence of instructions may be executed repeatedly, or under a given set of conditions a block of instructions may be skipped altogether. Typical instructions to modify the sequence of instructions after execution has begun may include, for example, LOOP and JUMP instructions.
Each instruction may include several fields, each of which is necessary to complete execution. These fields may include, for example, the operands for math operations, an address of an operand stored in memory, the register name holding an operand, the location of the next instruction to be executed, the number of times to execute an instruction loop. The processor parses each instruction, to determine instruction type and determine the number of fields in the instruction and the definition of each field. Then, the processor instructs appropriate functional units to execute their operation causing, for example, the addition unit to add two numbers or, causing a multiplier to multiply two numbers. As each instruction is executed, the processor fetches, or reads, the next instruction from memory and executes it.
Instruction execution speed is limited only by the speed of the underlying hardware. Often, however, external events may affect program execution or, the program may be event-driven. These external events may include, for example, striking a key on a keyboard or responding to a flag from a digital timer.
In some instances, program execution must be controlled temporally, or paced. For example, a sample may be read periodically from a monitoring device, such as monitoring combustion within an engine. In this example, a digital timer is programmed to periodically expire and generate a flag to interrupt the processor. Then, the processor begins executing a subroutine to read the monitoring device. This type of program execution is acceptable when timer accuracy and interrupt handling time requirements are not particularly stringent.
However, for applications where those tolerances are such that timing must be within a single microprocessor clock cycle, these prior art program execution methods are no longer acceptable. In particular, these prior art methods are unsatisfactory, for example when temporal precision is important, such as, for video compression/decompression, where large amounts of data may be stored, transported and displayed. Consequently, to reduce the video data volume, redundant information is commonly removed from the video, compressing the video data. Unfortunately, when the redundant information is removed, the temporal characteristic of the video content may be changed with the real-time nature of the video material being lost.
So, normally, to maintain the temporal relationship when the video is decompressed, timestamps are embedded into the video content. A typical timestamp is, essentially, time of day. The timestamps specify when a particular block of video data (most typically, a video frame) should be decompressed and/or displayed. As the video is compressed, the time of day is inserted into the compressed video content. When the video is decompressed, the timestamp is fetched by the decompression processor and provides a guide indicating when the video frame should be displayed. Thus, timestamp information embedded in data controls processor execution, temporally.
The timestamp method described above enables the temporal control of programs, but requires that timestamps be embedded in the content. Accordingly, this prior art method is unsuitable for applications where there is no content or where the time of execution must come from a source other than the content, such as when a master clock defines the execution time.
Another typical prior art method for temporally controlling program execution uses a digital timer. The digital timer is programmed to expire at a particular point in time. The processor is programmed to enter a no-op loop until the digital timer reaches the expiration count. The processor continues executing the no-op loop until the timer reaches the count and issues a flag, indicating the time has expired. The flag signals to the processor to interrupt the loop and to jump to another subroutine or program location.
While this prior art method of temporally controlling program execution is suitable for most current applications, it also is relatively inaccurate, and depends upon the time to initialize the timer and to complete the interrupt operation, which may vary significantly. Furthermore, where precision of a single microprocessor clock cycle is needed, these methods are unacceptable.
SUMMARY OF THE INVENTION
It is a purpose of the invention to enable programmers to precisely control execution timing.
It is another purpose of the present invention to enable programmers to precisely control temporal execution of multimedia computer programs.
The present invention is an apparatus and method of controlling instruction execution in the apparatus with a precise temporal execution arrangement. Accordingly, the preferred apparatus is a processor or microprocessor capable of executing a function-specific wait-state that is dependant upon a type specified by an instruction field. The microprocessor includes a reference clock counter that maintains the wait count, an instruction parser that strips the wait type and count from instructions and passes the stripped information to a comparator. The comparator compares the stripped information against the count. The wait types include: a relative timestamp type indicating execution at some time subsequent to the present cycle; a direct timestamp type indicating an absolute time for execution; and a timestamp range indicating a time period when execution is valid.
REFERENCES:
patent: 3928857 (1975-12-01), Carter et al.
patent: 4445177 (1984-04-01), Bratt et al.
patent: 5075849 (1991-12-01), Kuriyama et al.
patent: 5812074 (1998-09-01), Chung
patent: 5933626 (1999-08-01), Mahalingaiah et al.
patent: 5944841 (1999-08-01), Christie
patent: 6018776 (2000-01-01), Wise et al.
patent: 6041345 (2000-03-01), Levi et al.
patent: 6088784 (2000-07-01), Choquette
patent: 6167479 (2000-12-01), Hartnett et al.
patent: 6205250 (2001-03-01), Kranawetter
patent: 6263019 (2001-07-01), Ryan
patent: 6278735 (2001-08-01), Mohsenian
patent: 6292887 (2001-09-01), Janniello
Cao Chun
Fitch Even Tabin & Flannery
International Business Machines - Corporation
Lee Thomas
Percello Louis J.
LandOfFree
System and method for temporally controlling instruction... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for temporally controlling instruction..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for temporally controlling instruction... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2830504