Oscillators – Automatic frequency stabilization using a phase or frequency... – Plural oscillators controlled
Reexamination Certificate
2001-05-17
2003-03-25
Le, N. (Department: 2858)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Plural oscillators controlled
C331S00100A, C331S010000, C331S011000, C331S046000, C331S047000, C331S050000
Reexamination Certificate
active
06538516
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a system and method for synchronizing multiple phase-lock loops or other synchronizable oscillators without using a master clock signal.
2. Related Art
Many systems use synchronizable oscillators such as phase-lock loops (PLLs). In these systems, it is often desirable or necessary to synchronize the synchronizable oscillators. Synchronization of the synchronizable oscillators ensures that each synchronizable oscillator in a given system is operating at the same frequency.
An example of such a system is one in which multiple switching power supplies or converters are connected in parallel to provide a high current output (e.g., 15 to 200 A). Each converter in the system includes a PLL that sets the switching frequency of that converter's switches. Since each PLL in the system typically operates at a different free running frequency, the switching frequency of each converter's switches is different. This is undesirable because if the frequencies are close together, there will be low frequency beating at both the input and output degrading the performance of the power supply.
One conventional technique for synchronizing multiple PLLs is to have a predesignated master PLL provide a master clock signal to one or more slave PLLs. The slave PLLs can then lock to the master clock signal and thus operate at the same frequency as that of the master PLL. A limitation of this technique is that it is not fault tolerant. If the master PLL malfunctions or fails, the slave PLLs will operate at their free running frequencies, which are typically different. Thus, the PLLs will not be synchronized.
Accordingly, what is needed is a system and method for synchronizing multiple phase-lock loops or other synchronizable oscillators without using a master clock signal.
SUMMARY OF THE INVENTION
The present invention overcomes the disadvantages and limitations described above by providing a system and method for synchronizing multiple phase-lock loops or other synchronizable oscillators without using a master clock signal.
In one embodiment of the present invention, a method for synchronizing a plurality of synchronizable oscillators is provided. The method includes monitoring a respective output signal of each synchronizable oscillator, each output signal having a respective frequency, generating a synchronization signal based on the output signal having the highest frequency of all of the output signals, and providing the synchronization signal to all of the synchronizable oscillators.
In another embodiment of the present invention, a method for synchronizing a first synchronizable oscillator and a second synchronizable oscillator is provided. The method includes generating a first synchronization signal at a first synchronization circuit if the first synchronizable oscillator generates a first output signal before the second synchronizable oscillator generates a second output signal.
In another embodiment of the present invention, a system for synchronizing a first synchronizable oscillator and a second synchronizable oscillator is provided. The system includes a first synchronization circuit coupled to the first synchronizable oscillator, and a second synchronization circuit coupled to the second synchronizable oscillator. The first synchronization circuit is operable to generate a first synchronization signal if the first synchronizable oscillator generates a first output signal before the second synchronizable oscillator generates a second output signal.
In another embodiment of the present invention, a system is provided. The system includes a plurality of synchronizable oscillator, each synchronizable oscillator operating at a respective frequency, and synchronization means for synchronizing the plurality of synchronizable oscillators, the synchronization means operable to cause the plurality of synchronizable oscillators to operate at a frequency corresponding to the frequency of the synchronizable oscillator that is operating at the highest frequency.
In another embodiment of the present invention, a system is provided. The system includes a plurality of synchronizable oscillators, each synchronizable oscillator operable to generate a respective output signal, each output signal having a respective frequency, and a plurality of synchronization circuits, each synchronization circuit connected to a respective synchronizable oscillator and operable to generate a synchronization signal.
Other embodiments, aspects, and advantages of the present invention will become apparent from the following descriptions, the accompanying drawings, and the accompanying claims.
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Linear Technology Corporation,PolyPhase, High Efficiency, Synchronous Step-Down Switching Regulator, Initial Release Final Electrical Specifications LTC1629, Aug. 1999; pp. 1-24.
Fairchild Semiconductor Corporation
Hamdan Wasseem H.
Le N.
Skjerven Morrill LLP
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