Electrical computers and digital processing systems: processing – Processing control – Logic operation instruction processing
Reexamination Certificate
1999-03-31
2001-09-18
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Logic operation instruction processing
C712S244000, C712S245000, C712S213000
Reexamination Certificate
active
06292887
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to computer processors and, more particularly, to synchronizing instruction execution in a microprocessor or digital signal processor with external events.
2. Background Description
So-called superscalar Microprocessors and Digital Signal Processors operate by sequentially executing instructions which specify the individual operations, These sequential operations can include, for example, adding two numbers, subtracting numbers, multiplying numbers, moving data, performing boolean math, etc. A typical program for a microprocessor is, basically, a sequence of instructions written to perform a particular task.
Some program instructions may reorder instruction execution sequence on the fly. For example, a short sequence of instructions may be executed repeatedly or, under a given set of conditions, a block of instructions may be skipped altogether. Typical instructions to modify the sequence of instructions after execution has begun may include, for example, LOOP and JUMP instructions.
Each instruction may include several fields, each of which is necessary to complete execution. These fields may include, for example, the operands for math operations, an address of an operand stored in memory, the register name holding an operand, the location of the next instruction to be executed, the number of times to execute an instruction loop. The processor parses each instruction, to determine instruction type and to determine the number of fields in the instruction and the definition of each field. Then, the processor instructs appropriate functional units to execute their operation causing, for example, an addition unit to add two numbers or, causing a multiplier to multiply two numbers. As each instruction is executed, the processor fetches or reads, the next instruction from memory and executes it.
Instruction execution speed is limited only by the speed of the underlying hardware. Often, however external events may affect program execution or, the program may be event-driven. These external events may include, for example, striking a key on a keyboard or responding to a flag from a digital timer.
In some instances program execution must be controlled temporally, or paced. For example, a sample may be read periodically from a monitoring device, such as monitoring combustion within an engine. In this example, a digital timer is programmed to periodically expire and generate a flag that interrupts the processor. Then, the processor begins executing a subroutine to read the monitoring device. This type of program execution is acceptable when timer accuracy and interrupt handling time requirements are not particularly stringent.
However, for applications where timing tolerances are such that event timing must be to within a single microprocessor clock cycle, these prior art program execution methods are no longer acceptable. In particular, for example, these prior art methods are unsatisfactory when temporal precision is important such as, for video compression/decompression. Here, large amounts of data may need to be stored, transported and displayed. Consequently, to reduce the video data volume, redundant information is commonly removed from the video, compressing the video data. Unfortunately, when the redundant information is removed, the temporal characteristic of the video content may he changed, with the real-time nature of the video material being lost.
So, normally, when the video is decompressed, timestamps are embedded into the video content to maintain the temporal relationship. A typical timestamp is, essentially time of day. The timestamps specify when a particular block of video data (most typically, a video frame) should be decompressed and/or displayed. As the video is compressed, the time of day is inserted into the compressed video content. When the video is decompressed, the timestamp is fetched by the decompression processor and provides a guide indicating when the video frame should be displayed. Thus, the timestamp information, embedded in the data, temporally controls processor execution This timestamp method enables linking program control and execution to time.
Another prior art method for temporally controlling program execution uses a digital timer. The digital timer is set to count to or expire at a particular time at which point the timer issues a flag that indicates the time has expired. The processor is programmed to enter a no-op loop until the digital timer reaches the expiration count. The processor continues executing the no-op loop until the timer reaches the count, when the flag is issued. The flag signals to the processor to interrupt the loop and to jump to another subroutine or program location.
While these methods control program execution, maintaining responsiveness to external events, they also are relatively inaccurate, and their responsiveness depends, for example, upon the time to initialize the timer and to complete the interrupt operation, which may vary significantly. Furthermore, where precision to within a single microprocessor clock cycle is needed, these methods are unacceptable.
SUMMARY OF THE INVENTION
It is a purpose of the invention to enable programmers to precisely control execution timing in response to external events.
It is another purpose of the present invention to enable programmers to precisely link execution of computer programs to external events.
The present invention is an apparatus and method of synchronizing instruction execution in the apparatus with external events. Accordingly, the preferred apparatus is a processor or microprocessor capable of executing a function-specific wait-state in response to the occurrence of a particular external event. The type of function-specific wait-state is dependant upon a type specified by an instruction field. The microprocessor includes an event counter that maintains an event occurrence count, an instruction parser that strips the instruction type and event count from instructions and passes the stripped information to a comparator. The comparator compares the stripped information against an event count. The instruction types include: a relative type indicating execution at some event occurrence subsequent to the present cycle; a direct type indicating an absolute event occurrence count for execution; and an event range indicating a range of event occurrences wherein execution is valid.
REFERENCES:
patent: 3928857 (1975-12-01), Carter et al.
patent: 4445177 (1984-04-01), Bratt et al.
patent: 5216613 (1993-06-01), Head, III
Fitch Even Tabin & Flannery
International Business Machines Corp.
Pan Daniel H.
Percello Louis J.
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