Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-08-10
2001-09-04
Dharia, Rupal D. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S120000, C710S120000, C710S057000, C710S100000, C709S223000, C327S142000, C365S221000
Reexamination Certificate
active
06286072
ABSTRACT:
TECHNICAL FIELD
The present invention relates to bridges for interconnecting buses in a multiple bus computer environment, and more particularly, to a bridge into which is incorporated a system for synchronizing data transfers between asynchronous buses.
BACKGROUND ART
Computer systems typically include more than one bus, each bus in the system having devices attached thereto which communicate locally with each other over the bus. Examples of the different types of buses present in typical computer systems are a system bus to which a host central processing unit is attached and one or more peripheral buses. To permit system-wide communication between devices attached on different buses, bus-to-bus bridges or interfaces are provided to match the communications protocol of one bus with that of another.
Different bus-to-bus bridges are described in the following documents from IBM Corporation: Technical Disclosure Bulletin Vol. 38 No. 5, May 95, pp. 401-402 and EP 0 629 956 A2. These applications describe mechanisms which permit system-wide communication of devices attached to different buses in the system.
Each bus-to-bus bridge in a multi-bus computer system is used to connect two buses in the system. Various types of buses are available to construct a given computer system. One such bus which is becoming widely accepted is the PCI (Peripheral Component Interconnect) bus, which is capable of performing significant data transfer in a relatively short period of time (up to 120 megabytes of data per second). The PCI bus achieves this high level of performance, in part, because it may be directly linked to other high speed buses, such as system buses to which a CPU may be connected, and thus may provide for rapid transfer of data between devices attached to the PCI bus and devices attached to the system bus.
A typical architecture of a communication system which is used to transfer data between an emitter bus to a receiver bus includes a memory within the interface device which temporarily stores data received from the emitter bus before being unloaded to the receiver bus. Interfacing an emitter bus to a receiver bus is problematic when the two buses are asynchronous each other. A write operation performed to input data into the interface circuit is externally monitored by a write clock which is synchronous to the emitter bus clock, whereas a read operation performed to output data from the interface circuit is externally monitored by a read clock which is synchronous to the receiver bus clock.
Moreover to monitor each of the read and write operations inside the memory, a control signal is generated to indicate the status of the memory, e.g. if it is empty or not, and thus allowing or preventing a read or a write operation. If no data are stored thereby meaning that no read operations are to be performed, a flag ‘empty’ is asserted. When data are ready to be output a flag ‘not-empty’ is asserted.
In asynchronous systems wherein the read and write operations are independently clocked, the pulse duration of the flag ‘not-empty’ reflects the data traffic between the two buses. It is, therefore, mandatory that this control signal be accurate to clearly state to the receiver bus when data are available, and thus to perform the data transfer as efficiently as possible.
U.S. Pat. No. 5,506,809 discloses a system for generating such control signal named a status flag with the memory being a First-In- First-Out (FIFO) device. A write pointer indexed synchronously with a write clock signal is counting the available memory space for writing data into the FIFO and is compared to a read pointer indexed synchronously with a read clock signal, which counts the data to be output from the FIFO. The result of such comparison gives the value of the status flag. However, since two asynchronous clocks monitor both the read and the write operations within the FIFO, the status flag duration may be either shorter or longer than the receiver clock cycle, resulting in losing data or in the well-known metastability problem of the receiver system.
One common solution to this problem is to hold the flag pulse during at least one additional cycle whatever the value is (i.e. high level or low level), thereby ensuring that the receiver system has captured the valid level. However, such solutions are time consuming, which is not compliant with the high speed buses architectures, such as the Peripheral Component Interconnect (PCI) bus. Accordingly, it would be desirable to be able to provide a new system which eliminates the aforementioned problems.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a system which performs efficient data transfer between asynchronous buses. This object is achieved by employing a circuit which calibrates the width pulse of the memory status signal to the traffic of data being transmitted onto the receiver bus.
According to the present invention, a synchronization circuit for use in a bridge connecting an emitter bus operating on an emitter clock frequency to a receiver bus operating on a receiver clock frequency is provided. It is a feature of the invention that the synchronization circuit is responsive to a control signal generated by memory status means coupled to a memory which temporarily stores data transmitted from the emitter bus to the receiver bus. The control signal representative of the status of the memory is reflecting asynchronous read and write operations within the memory. The resulting signal output from the synchronization circuit is a one clock synchronized signal such that rising and falling transitions are synchronized to the receiver bus clock frequency.
In a preferred embodiment, the circuit comprises first detection means responsive only to falling transitions of the control signal for generating a first enabling signal, and second detection means responsive only to rising transitions of the control signal for generating a second enabling signal, whereby the first and second detection means being cross-coupled such that the first enabling signal operates as an enabling input to the second detection means and the second enabling signal operates as an enabling input to the first detection means. Moreover, clocked latching means are responsive to the first enabling signal and to the receiver bus clock for generating a clocked signal whereby the clocked signal operates as a restore input to the second detection means, and output means are responsive to the clocked signal and to the second enabling signal for generating the resultant synchronized signal.
In a preferred embodiment, the synchronization circuit is used in a bridge interfacing a PCI bus asynchronous to a Versa Module Eurocard (VME) bus, and the devices connected to each bus include audio or video boards, graphics controllers, SCSI controllers, PCMCIA controllers, or others I/O devices.
REFERENCES:
patent: 5473756 (1995-12-01), Traylor
patent: 5506809 (1996-04-01), Csoppenszky et al.
patent: 5673399 (1997-09-01), Guthrie et al.
patent: 5761427 (1998-06-01), Shah et al.
patent: 5790831 (1998-08-01), Lin et al.
patent: 5796963 (1998-08-01), Odom
patent: 5941964 (1999-08-01), Young et al.
patent: 5942924 (1999-08-01), Callahan
patent: 0 629 956 (1994-12-01), None
IBM Technical Disclosure Bulletin, vol. 38, No. 5, May 1995 “60X Bus-to-PCI Brfidge”.
Bredin Francis
Sitbon Claude
Dharia Rupal D.
International Business Machines - Corporation
McConnell Daniel E.
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