Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2001-12-06
2004-02-03
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S225700
Reexamination Certificate
active
06687170
ABSTRACT:
BACKGROUND OF THE INVENTION
In a memory circuit, such as a dynamic random access memory (DRAM) or a field programmable logic device, a plurality of memory cells are typically arranged in rows and columns for addressable access. For example, a DRAM chip may include 256 million or more cells, which are arranged in an array of rows (activated by word lines) or columns (activated by bit lines).
In a conventional DRAM chip, one or more of the millions of cells of the memory array may be defective. In order to avoid the need to discard an entire DRAM chip, redundant cells are provided that may be substituted for the one or more defective cells. Usually, if a particular cell in the memory array is determined to be defective, the entire row and column containing the defective cell is usually replaced by a redundant row and column. Herein, rows and columns of cells may be referred to as storage elements.
A conventional technique of substituting a defective storage element of the memory array with a replacement storage element involves using address fuses. Typically, each replacement storage element is associated with a bank of fuses. The address of a defective storage element is stored in the fuse bank so that calls to that address will activate the redundant storage element associated with the fuse bank.
Addresses are typically stored in the fuse bank by severing or maintaining the state of the individual fuses. Each fuse within an address fuse bank includes a fusible link which is capable of being severed (also “blown”) by the use of a laser or electrically by a high current. A value, such as a logical one (1) or zero (0), may be attributed to the fuse depending on whether the link remains connected or disconnected. In use, when a defective storage element of the memory array is addressed, a comparison of the incoming address and the address stored in the address fuses will match (there may be other fuses as well such as an enabling fuse) This indicates that the replacement storage element should be accessed instead of the defective storage element of the memory array.
Typical manufacturing processes perform a number of tests and operations to bypass defective storage elements with redundant storage elements. First, the chip is tested for defective storage elements. Second, for each storage element found to be defective, a redundant storage element is chosen. Third, a laser station blows some, none or all of the fuses of the redundant storage element's fuse bank to identify the address of the defective storage element.
Commercially-available laser stations tend not to be completely accurate. Occasionally, the laser will fail to sever a fusible link which should have been severed, may only partially sever a link which should have been severed, or may sever a link which should not have been severed. Similar problems tend to occur—and can occur more often—when blowing fuses electrically. Accordingly, some manufacturing processes recheck the chip by testing it again for defective storage elements. However, it substantially increases costs and processing times to do a full post-fuse test on every chip. Although processes exist which can physically scan the dies for failed fuses, these processes tend to be particularly difficult for DRAMS because DRAMS usually contain several fuse areas for different subunits of the die.
In view of the foregoing, there is a need in the art for a new system and method in which it is possible to quickly determine whether the fuses within a fuse bank accurately represent the information they are supposed to store.
SUMMARY OF THE INVENTION
The present invention addresses this need among others.
One aspect of the invention provides a system for determining the accuracy of address fuses. The system includes a memory including addressable storage elements; address fuses whereby each fuse includes a link in a connected or disconnected state and the collective state of the address fuses identifies an address value; a parity fuse whereby the fuse includes a link in a connected or disconnected state and the state of the parity fuse represents a parity value, the parity value being based on, but not equivalent to, the address of an addressable storage element, and; an output providing a value dependant upon the address value and the parity value.
Another aspect of the invention is a memory having: a memory including addressable storage elements; a fuse bank whereby the state of a first set of the fuses defines a first value and the state of a second set of fuses defines a second value based on the address of a defective storage element; and digital logic circuits structured and arranged to generate a signal indicative of whether the value defined by the first set of fuses is different from the address of the defective storage element, the signal being based on the state of the first and second set of fuses.
Yet a further aspect of the invention involves a method of manufacturing a die. It includes providing the address of a storage element in memory; providing a test value dependant on the address; determining which, if any, address fuses on the die should be blown based on the address; determining which, if any, other fuses on the die should be blown based on the test value; blowing fuses based on such determinations; and determining the accuracy of the step of blowing fuses including comparing the state of the address fuses with the state of the other fuses.
A still further aspect of the invention provides a system for determining whether information actually stored on a device matches information that was to be stored on the device. The system includes a plurality of fuses, each fuse having a connected state and a disconnected state; a first set of the fuses being such that the state of the fuses in the first set represents the information actually stored on the device; a second set of fuses being such that the state of the fuses in the second set represents information which is a function of the information that was to be stored on the device; and means for comparing the information represented by the first set of fuses against the information represented by the second set of fuses.
The means for comparing the values representative of the fuse states is not limited to any particular structure or arrangement. By way of example only, it may be comprised of an interconnected collection of digital logic elements, an analog circuit, or a processor which manipulates and transfers data in accordance with a program.
The methods and systems are similarly not limited in the type of information which may be used to confirm the accuracy of the information stored in the fuses. For example, if one set of fuses represents information, the other set of fuses may represent a value indicative of the information's parity. This may include even parity, odd parity, a Hamming code or some other testing function.
Other aspects, features, advantages, etc., will be apparent to one skilled in the art when the disclosure herein is taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5835431 (1998-11-01), Miner et al.
patent: 5859801 (1999-01-01), Poechmueller
patent: 5883903 (1999-03-01), Higashitani
patent: 5999463 (1999-12-01), Park et al.
patent: 6430101 (2002-08-01), Toda
Petter Robert
Zimmerman Ulrich
Elms Richard
Infineon Technologies Richmond LP
Lerner David Littenberg Krumholz & Mentlik LLP
Phung Anh
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