Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to generate an address of a microroutine
Reexamination Certificate
1998-12-30
2002-01-08
Donaghue, Larry D. (Department: 2154)
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to generate an address of a microroutine
C712S213000
Reexamination Certificate
active
06338132
ABSTRACT:
FIELD
The present invention is directed to improvements in instructions to be processed in a processor.
BACKGROUND INFORMATION
Program instructions control the operation of modern microprocessors. Typically, each program instruction includes a specification of the operation to be performed, the type of operands to be manipulated, and the location of these operands. A typical instruction comprises one to several programming elements. The arrangement of these programming elements is referred to as an instruction format. There are various instruction formats to implement different functionalities for any number of different microprocessors and within a single microprocessor there may be various instruction formats based on the number and type of programming elements used to comprise each instruction.
One example microprocessor, the Intel Pentium® Pro microprocessor, recognizes various programming elements including, for example, opcodes, immediate operands, register specifiers, memory operands, scale/index/base (SIB) registers, prefixes, displacement and addressing-mode specifiers. These programming elements, either alone or in combination with other programming elements, perform a specified function when included in an instruction. For example, a register specifier specifies either a source register operand and/or a destination register operand. An example instruction comprised of (MOV A, B) is used to move a value from a source register operand (B) to a destination register operand (A).
In the above example, the programming element specifying the move function (MOV), is the opcode. The opcode specifies the operation performed by the instruction. An opcode is typically contained in each instruction, although it is not a requirement. Opcodes can specify numerous operations including, for example, moving, adding, subtracting, multiplying, dividing and storing. Some operations may have several different opcodes, each specifying a different variant of the operation, for example, an exclusive or (XOR) and a logical or (OR). Thus, by combining an opcode and one or more of the other programming elements, a complete instruction can be formed.
The processor does not understand symbolic instructions such as the example above, MOV A, B, but rather understands only bits or a series of bits. An assembler or compiler converts the symbolic instructions, usually generated using a higher level language such as the C programming language, into a long series of bits, termed binary code or machine language. In certain microprocessors, for example complex instruction set computer (CISC) processors, the instruction is further converted to a more basic unit termed a micro-op in order to be executed.
One of the programming elements listed above is an immediate operand. The immediate operand is a value included at the time of programming and is part of the program code. Unlike the example above, where the source register is the address of the value to be moved, an immediate operand is the actual value on which the operation specified by the opcode is to be performed. For example, a symbolic instruction of (MOV A, 512) is used to move the value 512 to a destination register operand (A).
A typical instruction or micro-op includes a fixed number of bits, regardless of the information to be stored in each instruction.
FIG. 1
shows the format of an example instruction
100
in a conventional instruction format. The instruction includes an opcode field
101
and an immediate operand field
102
. In this particular instruction format the opcode field
101
has a bit length of X and the immediate operand field
102
has a bit length of Y. The fixed number of bits allocated to each instruction may be determined by the maximum number of bits employed for each of the above listed programming elements. For example, the maximum number of bits for the opcode is known because the number of operations specified by the opcode is fixed. For example, if 6 bits are designated for the opcode field
101
, there can be a maximum of 2
6
or 64 operations specified by the opcode, and each of these operations will be represented by a unique combination of the 6 bits. The fixed length of the bits (Y) allocated to the immediate operand field
102
is normally equal to the size of the maximum immediate operand that will occur in any instruction. For example, if the maximum immediate operand is 32 bits in length, each instruction will have a fixed length of 32 bits assigned for the immediate operand, regardless of whether 32 bits are employed for that particular instruction. Thus, each and every instruction formatted in the above described instruction format will have 6 bits allocated to the opcode field
101
and 32 bits allocated to the immediate operand field
102
, regardless of whether these bits are employed to express the function to be performed by the instruction.
The above described instruction or micro-op that includes an opcode and an immediate operand works reasonably well and is an efficient use of allocated bits when the immediate operand is its maximum size. However, in the case of the average instruction, there will be no immediate operand or the immediate operand will employ less bits than the number of allocated bits. In this average case, the bits assigned to the immediate operand are wasted because the remainder of the allocated bits are unused. This was not a problem in previous implementations because the processor was only holding a few instructions or micro-ops at any given time, however modem processors can hold thousands of instructions or micro-ops causing the space employed by these instructions to become substantial.
SUMMARY
An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field.
REFERENCES:
patent: 5745722 (1998-04-01), Matsumoto et al.
patent: 5819058 (1998-10-01), Miller et al.
patent: 5896519 (1999-04-01), Worrell
patent: 5915109 (1999-06-01), Nakakimura et al.
patent: 6038657 (2000-03-01), Favor et al.
Ahuja Hitesh
Alexander William
Hammarlund Per
Krick Robert F.
Kyker Alan B.
Donaghue Larry D.
Intel Corporation
LandOfFree
System and method for storing immediate data does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for storing immediate data, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for storing immediate data will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2833921