System and method for skew compensating a clock signal and...

Details System and method for skew compensating a clock signal and... System and method for skew compensating a clock signal and...

2001-08-29

2003-09-09

Phan, Trong (Department: 2818)

Static information storage and retrieval

Systems using particular element

Multiaperture cell

C365S155000, C365S158000, C365S161000

Reexamination Certificate

active

06618283

ABSTRACT:

TECHNICAL FIELD
This invention relates to electronic devices that are operated in synchronism with a clock signal, and more particularly to a system and method for compensating for variations in the propagation delay of clock signals in comparison to the propagation delay of other signals.
BACKGROUND OF THE INVENTION
The operating speed of electronic devices, such as memory devices, can often be increased by synchronizing the operation of the device to a clock signal. By operating the device synchronously, the timing at which various function occur in the device can be precisely controlled thereby allowing the speed at which these functions are performed to be increased by simply increasing the frequency or speed of the clock signal. However, as the speeds of clock signals has continued to increase with advances in semiconductor fabrication techniques, the propagation delays of clock signals within integrated circuit devices have become a problem. More specifically, internal clock signals are often generated from an external clock signal applied to the integrated circuit device. These internal clock signals are coupled throughout the integrated circuit device to control the timing of a variety of circuits. The times required for the internal clock signals to propagate to these circuits is difficult to either control or predict. As clock speeds continue to increase, the unpredictable and/or uncontrolled variations in internal clock signal propagation times can cause internal clock signals to be applied to circuits either too early or too late to allow the circuits to properly perform their intended functions. This problem, known as “clock skew,” threatens to limit the speed at which integrated circuit devices can function.
Various solutions have been proposed to address this clock skew problems. Some of these solutions are described in Takanori Saeki et al., “A Direct-Skew-Detect Synchronous Mirror Delay for Application-Specific Integrated Circuits,”
IEEE Journal of Solid
-
State Circuits,
Vol. 34, No. 3, March 1999. The article by Takanori Saeki et al. describes both open-loop and closed-loop clock skew compensation approaches. Closed-loop approaches include the use of phase-locked loops (“PLL”) and delay-locked loops (“DLL”) to synchronize the phase or timing of an internal clock signal to the phase or timing of an external clock signal used to generate the internal clock signal. These closed-loop approaches use a feedback signal to indicate the timing variations within the device. A phase comparator, such as a phase detector, is required to compare the phase or timing of the feedback signal to the phase or timing of a reference signal. Unfortunately, a significant amount of time may be required to achieve lock of the PLL or DLL.
Open-loop designs described in the Takanori Saeki et al. article include synchronized mirror delay (“SMD”) circuits and clock synchronized delay (“CSD”) circuits. CSD circuits generally include a variable delay line, usually a series of inverters, and latch circuits for selecting the output of one of these inverters as the delay line output. An internal clock signal is applied to the CSD circuit, and the magnitude of the delay provided by the CSD circuit is controlled in an attempt to set the phase or timing at which the internal clock signal is applied to an internal circuit. SMD circuits are basically the same as CSD circuits except that CSD circuits require the use of latches to store information. On the other hand, SMD circuits require specially shaped input clock signals. In order to generate internal clock signals on both the rising and falling edges of a clock signal (i.e., double data rate operation), SMD circuits, but not CSD circuits, require two variable delay lines, one for the clock signal and one for its compliment. In view of the similarity of CSD circuits and SMD circuits, they will be generically referred to herein as CSD/SMD circuits.
A conventional CSD/SMD circuit
10
described in the Takanori Saeki et al. article is shown in FIG.
1
. An external clock signal XCLK is applied to an input buffer
12
, and the output of the buffer
12
is applied to a delay model circuit
14
. The output of the delay model circuit
14
is coupled through a measurement delay line to set a delay of a variable delay line
20
. The delay of both the measurement delay line
16
and the variable delay line
20
is set to integer multiples of a clock period of the external clock signal less the delay of the delay model circuit
14
, i.e., n*tCLK−d
mdl
, where n is an integer, tCLK is the period of the XCLK signal, and d
mdl
is the delay of the delay model circuit
14
. The variable delay line
20
outputs a clock signal to a clock driver
24
. The clock driver
24
then outputs an internal clock signal ICLK to an internal clock line
28
. The internal clock line
28
is coupled to a number of internal circuits
32
through respective circuit paths, which are collectively known as a “clock tree”
36
.
The external clock signal XCLK is coupled through the input buffer
12
with a delay of d
1
, through the measurement delay line
16
with a delay of d
2
, through the variable delay line
20
with a delay of d
3
, and through the clock driver
24
with a delay of d
4
. For the phase of the internal clock signal ICLK to be synchronized to the phase of the external clock signal XCLK before the CSD/SMD circuit
10
has been locked, the sum of these delays, i.e., d
1
+d
mdl
+d
2
+d
3
+d
4
, should be equal to integer multiples of one period tCLK of the external clock signal XCLK.
In operation, the delay d
3
of the variable delay line
20
is set in a conventional manner so that it is equal to the delay of the measurement delay line
16
. The delay d
2
of the measurement delay line
16
is set by conventional means to the difference between integer multiples of the period tCLK of the external clock signal XCLK and the delay d
mdl
of the delay model circuit
14
, i.e., d
2
=n*tCLK−d
mdl
. Thus, after one clock period tCLK, the delay d
3
of the variable delay line
20
has been determined. The total delay from the input of the input buffer
12
to the internal clock line
28
is given by the equation: d
1
+d
3
+d
4
. The delay d
mdl
of the delay model circuit
14
is set to the sum of the delay d
1
of the input buffer
14
and the delay d
4
of the clock driver
24
. This can be accomplished by implementing the delay model circuit
14
with a “dummy” input buffer
42
and a “dummy” clock driver
44
. The dummy input buffer
42
is preferably identical to the input buffer
12
and thus also provides a delay of d
1
. Similarly, the dummy clock driver
44
is preferably identical to the clock driver
24
and thus also produces a delay of d
4
. Using the equation d
3
=d
2
=n*tCLK−d
mdl
, the above equation d
1
+d
3
+d
4
for the total delay can be rewritten as: d
1
+n*tCLK−d
mdl
+d
4
. Combining this last equation and the equation d
mdl
=d
1
+d
4
allows the equation for the total delay from the input of the input buffer
12
to the ICKL line
28
to be rewritten as: d
1
+n*tCLK−d
1
−d
4
+d
4
. This last equation can be reduced to simply n*tCLK, or 1 clock period of the external clock signal XCLK, assuming the delay of the delay model circuit
14
is less than a period of the external clock signal, i.e., d
mdl
<tCLK. Thus, by using the delay model circuit
14
to model the delay d
1
of the input buffer
12
and the delay d
4
of the clock driver
24
, the phase of the internal clock signal ICLK can be synchronized to the phase of the external clock signal XCLK. Moreover, the total lock time, including the delay through the delay model circuit
14
and the measurement delay line
16
, is equal to d
1
+d
mdl
+d
2
+d
3
+d
4
, which can be reduced to 2n*tCLK. Therefore, this phase matching of the ICLK signal can be accomplished after only two periods of the external clock XCLK signal so that the integer “n” may be

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